1 //----------------------------------------------------------------------------
3 //----------------------------------------------------------------------------
13 // SelectMAP interface ports
15 RDWR_B, // Read/write signal
17 INIT_B, // Initialization/interrupt signal
18 CCLK, // Local CCLK output
22 // User clock/reset ports
26 // SelectMAP protocol ports
39 wire [0:31] LoopDataW;
52 // synthesis attribute tig of activate_r is yes;
54 // synthesis attribute tig of activate_a is yes;
57 wire [7:0] write_data;
75 reg [7:0] root_in_d_reg;
82 root my_root(User_Clk, root_in_r, root_in_a, root_in_d,
83 root_out_r, root_out_a, write_data);
85 assign root_out_a = root_out_a_reg;
86 assign root_in_r = root_in_r_reg;
87 assign read_enable = read_enable_reg;
88 assign write_enable = write_enable_reg;
89 assign root_in_d = root_in_d_reg;
92 always @(posedge User_Clk)
95 if (root_out_r && !root_out_a_reg && !write_full) begin
98 end else if (root_out_a_reg && !root_out_r) begin
101 gpleds_reg[4] = write_enable_reg;
102 gpleds_reg[5] = root_out_r;
103 gpleds_reg[6] = root_out_a_reg;
107 always @(posedge User_Clk)
110 if (!read_empty && !root_in_r_reg && !root_in_a) begin
112 root_in_d_reg = read_data;
119 gpleds_reg[1] = read_enable_reg;
120 gpleds_reg[2] = root_in_r_reg;
121 gpleds_reg[3] = root_in_a;
124 assign gpleds = gpleds_reg;
139 OBUF obuf_cclk( .I( CCLK_int ),
143 IOBUF iobuf_d0( .I( D_O[0] ),
149 IOBUF iobuf_d1( .I( D_O[1] ),
155 IOBUF iobuf_d2( .I( D_O[2] ),
161 IOBUF iobuf_d3( .I( D_O[3] ),
167 IOBUF iobuf_d4( .I( D_O[4] ),
173 IOBUF iobuf_d5( .I( D_O[5] ),
179 IOBUF iobuf_d6( .I( D_O[6] ),
185 IOBUF iobuf_d7( .I( D_O[7] ),
191 // Clock buffer and reset
192 IBUFGDS_LVDS_25 diff_usrclk_buf( .I( Clkin_p ),
203 defparam rst0.INIT = 1'b1;
205 FD rst1( .D( rst[0] ),
209 defparam rst1.INIT = 1'b1;
211 FD rst2( .D( rst[1] ),
215 defparam rst2.INIT = 1'b1;
217 FD rst3( .D( rst[2] ),
221 defparam rst3.INIT = 1'b1;
223 assign User_Rst = |rst;
226 // FIFO module instantiation
228 .WrFifo_Din( write_data ),
229 .WrFifo_WrEn( write_enable ),
230 .WrFifo_Full( write_full ),
232 .RdFifo_Dout( read_data ),
233 .RdFifo_RdEn( read_enable ),
234 .RdFifo_Empty( read_empty ),
236 .User_Rst( User_Rst ),
237 .User_Clk( User_Clk ),
238 .Sys_Rst( User_Rst ),
239 .Sys_Clk( User_Clk ),