3 module root(clk, in_r, in_a_, in_d,
4 out_r_, out_a, out_d_);
8 `input(in_r, in_a, in_a_, [7:0], in_d)
9 `output(out_r, out_r_, out_a, [7:0], out_d_)
11 `defreg(horn_in_r_, [0:0], horn_in_r)
12 `defreg(horn_in_d_, [(`PACKET_WIDTH-1):0], horn_in_d)
13 `defreg(funnel_out_a_, [0:0], funnel_out_a)
15 reg [(`DATAWIDTH-1):0] out_d;
16 assign out_d_ = out_d[7:0];
26 initial count_out = 0;
28 wire [(`DATAWIDTH-1):0] funnel_out_d;
29 fabric fabric(clk, horn_in_r_, horn_in_a, horn_in_d_,
30 funnel_out_r, funnel_out_a_, funnel_out_d);
33 always @(posedge clk) begin
36 horn_in_d = (horn_in_d << 8) | in_d;
37 count_in = count_in + 1;
38 if (count_in >= 6) full_in = 1;
42 `onwrite(horn_in_r, horn_in_a)
51 always @(posedge clk) begin
53 `onread(funnel_out_r, funnel_out_a)
59 `onwrite(out_r, out_a)
61 count_out = count_out - 1;
62 if (count_out==0) full_out = 0;