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\usepackage{bytefield1}
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\author{
\normalsize{
\begin{tabular}{c}
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}

\title{\vspace{-1cm}The FleetTwo Dock}

\begin{document}

\maketitle

\begin{abstract}
\end{abstract}

\vfill

\begin{center}
\epsfig{file=overview,width=1.5in}
\epsfig{file=ports,width=1.5in}
\epsfig{file=best,width=1.5in}
\end{center}

\pagebreak

\section{Overview of Fleet}

A Fleet processor consists of a {\it switch fabric} with several
functional units called {\it ships} connected to it.  At each
connection between a ship and the switch fabric lies a programmable
element known as the {\it dock}.

A {\it path} specifies a route through the switch fabric from a
particular {\it source} to a particular {\it destination}.  The
combination of a path and a single word {\it payload} is called a {\it packet}.  The
switch fabric carries packets from their sources to their
destinations.  Each dock has two destinations: one for {\it
  instructions} and one for {\it data}.  A Fleet is programmed by
depositing packets into the switch fabric; these packets' paths lead
them to the instruction destinations of the docks.

When a packet arrives at the instruction destination of a dock, it is
enqueued for execution.  Before the instruction executes, it may cause
the dock to wait for a packet to arrive at the dock's data destination
or for a value to be presented by the ship.  It may present a data
value to the ship or transmit it for transmission to some other
destination.

When an instruction sends a packet into the switch fabric, it may
specify that the payload of the packet is irrelevant.  Such packets
are known as {\it tokens}, and consume less energy than data packets.
From a programmer's perspective, a token packet is indistinguishable
from a data packet with a unknown payload.

\begin{center}
\epsfig{file=overview,width=4in}\\
{\it Overview of a Fleet processor}
\end{center}

\pagebreak

\section{The Ship-Switch Fabric Interface}

The diagram below represents a {\it programmer's} conceptual view of
the interface between ships and the switch fabric.  Actual
implementation circuitry may differ substantially.  Sources and
destinations that can send and receive only tokens -- not data items
-- are drawn as dashed lines.

\begin{center}
\epsfig{file=ports,width=4in}\\
{\it The interface betwen the switch fabric and the ship}
\end{center}

The term {\it port} refers to an interface to the ship, the {\it
  dock} connecting it to the switch fabric, and the corresponding
sources and destinations on the switch fabric.

Each dock consists of a {\it data latch}, which is as wide as a
single machine word and a {\it pump}, which is a circular fifo of
instruction-width latches.  The values in the instruction fifo
control the data latch.

Note that the pump in each dock has a destination of its own; this is
the {\it instruction destination} mentioned in the previous section.
Note that unlike all other destinations, there is no buffering fifo
guarding this one.  The size of these fifos are exposed to the
software programmer so she can avoid deadlock.

\pagebreak

\section{The FleetTwo Pump}

The diagram below shows the datapath for the FleetTwo pump circuitry.
The square box marked {\tt D} on the output from the {\tt IH} latch is
the instruction decoder, which decodes word-width instructions into a
set of control signals suitable for operating the pump.  The boxes
marked {\tt CD} are carry detectors.  These detect zero values in the
count and also generate the partial differences used in the decrement
operation.

\begin{center}
\epsfig{file=best,width=4in}\\
{\it The pump datapath}
\end{center}

The latches of primary interest here are:
\begin{itemize}
\item {\tt IH}: Instruction Horn (leaf node; may be shared)
\item {\tt F0}: Fifo Stage 0 (first fifo stage)
\item {\tt OD}: On Deck
\item {\tt F}: Flags, {\tt NF}: Next Flags
\item {\tt P}: Path (the path to use for outbound data/tokens)
\item {\tt D}: Data
\item {\tt DP}: Data Predecessor (ship for output ports, switch fabric for input ports)
\item {\tt DS}: Data Successor (switch fabric for output ports, ship for input ports)
\item {\tt RC}: Repeat Count, {\tt NRC}: Next Repeat Count
\item {\tt LC}: Loop Count, {\tt NLC}: Next Loop Count
\end{itemize}

Each instruction that executes causes the latches of the pump to fire
in two phases, denoted as the ``left phase'' and the ``right phase''.
In the diagram, the left phase latches are those to the left of the
vertical line down the center, and the right phase latches are to the
right.  Therefore each instruction execution requires two GasP
pipeline stages to complete.

\subsection{Flags}

The pump has four flags: {\tt A}, {\tt B}, {\tt S}, {\tt Z}.  Of
these four, only the first two may be modified directly by
instructions.

\begin{itemize}
\item The {\tt A} and {\tt B} flags are general-purpose flags which
      may be set and cleared by the programmer.

\item The {\tt S} flag, known as the {\it summary} flag.  Its value is
      determined by the ship, but unless stated otherwise, it should
      be assumed that whenever the 37th bit of the data ({\tt D})
      latch is loaded, that same bit is also loaded into the {\tt S}
      flag.  This lets the ship make decisions based on whether or not
      the top bit of the data latch is set; if two's complement
      numbers are in use, this will indicate whether or not the
      latched value is negative.

\item The {\tt Z} flag, known as the {\it zero} flag, is set whenever
      the value in the loop counter ({\tt LC}) is zero.  This flag can
      be used to perform certain operations (such as sending a
      completion token) only on the last iteration of a loop.
\end{itemize}

Many instruction fields are specified as two-bit {\it predicates}.
These fields contain one of four values, indicating if an action
should be taken unconditionally or conditionally on one of the {\tt A}
or {\tt B} flags:

\begin{itemize}
\item {\tt 00:} if {\tt A} is set
\item {\tt 10:} if {\tt B} is set
\item {\tt 01:} if {\tt Z} is set ({\tt LC=0})
\item {\tt 11:} always
\end{itemize}

\pagebreak
\section{Instructions}

In order to cause an instruction to execute, the programmer must first
cause that instruction word to arrive in the data latch of some output
dock.  For example, this might be the ``data read'' output dock of the
memory access ship or the output of a fifo ship.  Once an instruction
has arrived at this output dock, it is {\it dispatched} by sending it
to the {\it instruction port} of the dock at which it is to execute.

Each instruction is 26 bits long, which makes it possible for an
instruction and an 11-bit path to fit in a single word of memory.
This path is the path from the {\it dispatching} dock to the {\it
  executing} dock.

\setlength{\bitwidth}{3.5mm}
{\tt \footnotesize
\begin{bytefield}{37}
  \bitheader[b]{0,25,26,36}\\
  \bitbox{11}{dispatch path} 
  \bitbox{26}{instruction} 
\end{bytefield}}

{\bf Note:} the instruction encodings below are simply ``something to
shoot at'' and a sanity check to make sure we haven't overrun our bit
budget.  The final instruction encodings will probably be
different.

All instructions other than {\tt interrupt}, {\tt massacre}, {\tt clog},
and {\tt unclog} have the following format:

\setlength{\bitwidth}{3.5mm}
{\tt \footnotesize
\begin{bytefield}{37}
  \bitheader[b]{0,21,22,23,24,25,26,36}\\
\color{light}
  \bitbox{11}{dispatch path} 
\color{black}
  \bitbox{1}{IM} 
  \bitbox{1}{DL} 
  \bitbox{2}{P} 
\color{light}
  \bitbox[tbr]{22}{} 
\color{black}
\end{bytefield}}

The abbreviation {\tt IM} stands for {\it Interruptible/Massacreable}.
An {\tt interrupt} or {\tt massacre} instruction will not execute
until an instruction with the {\tt IM} bit is present at the head of
the instruction fifo.

The abbreviation {\tt DL} stands for {\it Decrement Loop}; if this bit
is set, the loop counter decrements.  Once an instruction has
finished executing (including repeating, if applicable), the
instruction will reloop if the loop count ({\tt LC}) value was
greater than zero {\it prior to decrementing}.

The abbreviation {\tt P} stands for {\it predicate}; this is a two-bit
code that indicates if the instruction should be executed or ignored.
If an instruction is ignored, it might still reloop.

\pagebreak
\subsection{RePeating and ReLooping}

\begin{table}[htp]
\centering
\begin{minipage}{3in}
\centering
\begin{center}
\begin{tabular}{|r|c|c|}\hline
                      &  RePeating? & ReLooping? \\\hline
{\tt send}            &  Y      &  Y   \\\hline
{\tt literal}         &  N      &  Y   \\\hline
{\tt flags}           &  N      &  Y   \\\hline
{\tt repeat}          &  N      &  Y   \\
{\tt loop}            &  N      &  Y
\footnote{note, however, that the decision to reloop or not is based on the value in the loop counter {\it before} execution of the {\tt loop} instruction}
\\
{\tt takeLoopCounter}   &  N      &  Y   \\
{\tt takeRepeatCounter} &  N      &  Y   \\
\hline
{\tt clog}            &  N      &  N   \\
{\tt unclog}          &  n/a    &  n/a \\
{\tt interrupt}       &  n/a    &  n/a \\
{\tt massacre}        &  n/a    &  n/a \\\hline
\end{tabular}
\end{center}
\end{minipage}
\caption{classification of instructions}
\end{table}

{\bf RePeating}\\
An instruction will repeat if it is classified as a repeating
instruction and the repeat counter is nonzero.  Instructions
non-repeating instructions have no effect on the repeat
counter (except for {\tt repeat}, of course).

{\bf ReLooping}\\
An instruction reloops if {\bf all} of the following are true:
\begin{enumerate}
\item The repeat counter has reached zero.
\item The instruction is a ``relooping instruction'' as shown below.
\item The loop counter is greater than zero.  This check takes into
      account the result of a {\tt literal} instruction, but does not
      take into account the effect of the {\tt DL} bit.
\end{enumerate}
{\it Important:} if an instruction is {\it not} going to reloop
(according to the rules above), it must execute even if the tail of
the instruction fifo is occupied (full).


\pagebreak
\subsection{{\tt send} (variants: {\tt sendto}, {\tt dispatch})}

\setlength{\bitwidth}{5mm}
{\tt
\begin{bytefield}{26}
  \bitheader[b]{12-16,19,21}\\
\color{light}
  \bitbox{1}{IM}
  \bitbox{1}{DL}
  \bitbox{2}{P}
\color{black}
   \bitbox{3}{001} 
\color{light}
  \bitbox[trb]{2}{} 
\color{black}
  \bitbox{1}{\tt Ti}
  \bitbox{1}{\tt Di}
  \bitbox{1}{\tt Dc}
  \bitbox{1}{\tt Do}
  \bitbox{1}{\tt To}
  \bitbox[l]{17}{}
\end{bytefield}}

%\begin{bytefield}{26}
%  \bitheader[b]{12-18}\\
%  \bitbox[]{8}{\raggedleft Input Dock:}
%  \bitbox[r]{2}{}
%  \bitbox{1}{\tt So} 
%  \bitbox{1}{\tt Dc}
%  \bitbox[l]{15}{}
%\end{bytefield}
%
%\begin{bytefield}{26}
%  \bitheader[b]{12-18}\\
%  \bitbox[]{8}{\raggedleft Output Dock:}
%  \bitbox[r]{2}{}
%  \bitbox{1}{\tt Si}
%  \bitbox{1}{\tt To}
%  \bitbox[l]{15}{}
%\end{bytefield}

\begin{bytefield}{26}
  \bitheader[b]{0,10,11}\\
  \bitbox[1]{13}{\raggedleft {\tt sendto} ({\tt LiteralPath\to Path})}
  \bitbox[r]{1}{}
  \bitbox{1}{\tt 1}
  \bitbox{11}{\tt LiteralPath}
\end{bytefield}

\begin{bytefield}{26}
  \bitheader[b]{10,11}\\
  \bitbox[1]{13}{\raggedleft {\tt dispatch} ({\tt DP[37:27]\to Path})\ \ }
  \bitbox[r]{1}{}
  \bitbox{1}{\tt 0}
  \bitbox{1}{\tt 1}
\color{light}
  \bitbox[trb]{10}{}
\color{black}
\end{bytefield}

\begin{bytefield}{26}
  \bitheader[b]{10,11}\\
  \bitbox[1]{13}{\raggedleft {\tt send} ({\tt Path} unchanged):}
  \bitbox[r]{1}{}
  \bitbox{1}{\tt 0}
  \bitbox{1}{\tt 0}
\color{light}
  \bitbox[trb]{10}{}
\color{black}
\end{bytefield}

\begin{itemize}
\item {\tt Ti} - Token Input: wait for the token predecessor to be full and drain it.
\item {\tt Di} - Data Input: wait for the data predecessor to be full and drain it.
\item {\tt Dc} - Data Capture: pulse the data latch.
\item {\tt Do} - Data Output: fill the data successor.
\item {\tt To} - Token Output: fill the token successor.
\end{itemize}

The {\tt F0}, {\tt DS}, and {\tt TS} stages must all be empty in order for an
instruction to execute.

The repeat counter can hold a number {\tt 0..MAX} or a special value
$\infty$.  If the repeat count ({\tt RC}) holds a value other than
$\infty$, it is latched with {\tt max(RC-1, 0)}.  If the repeat
counter reaches zero, the instruction ceases executing and either
reloops or retires (see earlier section for details).


\pagebreak
\subsection{{\tt data}, {\tt datahi}, {\tt datalo}}

These instructions load part or all of the data latch ({\tt DL}).

{\tt datahi: Literal[18:1]\to D[37:20]} (and {\tt Literal[18]\to S})

\setlength{\bitwidth}{5mm}
{\tt
\begin{bytefield}{26}
  \bitheader[b]{0,18,19,21}\\
\color{light}
  \bitbox{1}{IM} 
  \bitbox{1}{DL} 
  \bitbox{2}{P}
\color{black}
  \bitbox{1}{0} 
  \bitbox{2}{11} 
\color{light}
  \bitbox[trb]{1}{} 
\color{black}
  \bitbox{18}{Literal} 
\end{bytefield}}

{\tt datalo: Literal[19:1]\to D[19:1]}

\setlength{\bitwidth}{5mm}
{\tt
\begin{bytefield}{26}
  \bitheader[b]{0,18,19,21}\\
\color{light}
  \bitbox{1}{IM} 
  \bitbox{1}{DL} 
  \bitbox{2}{P}
\color{black}
  \bitbox{1}{0} 
  \bitbox{2}{10} 
  \bitbox{19}{Literal} 
\end{bytefield}}

{\tt data:}

\setlength{\bitwidth}{5mm}
{\tt
\begin{bytefield}{26}
  \bitheader[b]{0,18,19,21}\\
\color{light}
  \bitbox{1}{IM} 
  \bitbox{1}{DL} 
  \bitbox{2}{P}
\color{black}
  \bitbox{1}{1} 
  \bitbox{2}{SEL} 
  \bitbox{19}{Literal} 
\end{bytefield}}

{\tt
\begin{tabular}{|r|c|c|c|}\hline
sel  & D[37:20]      & D[19:1]       \\\hline
00  & Literal[18:1] & all 0         \\
01  & Literal[18:1] & all 1         \\
10  & all 0         & Literal[19:1] \\
11  & all 1         & Literal[19:1] \\
\hline
\end{tabular}}




\subsection{{\tt flags}}

\setlength{\bitwidth}{5mm}
{\tt
\begin{bytefield}{26}
  \bitheader[b]{0,7,8,15,16-19,21}\\
\color{light}
  \bitbox{1}{IM} 
  \bitbox{1}{DL} 
  \bitbox{2}{P}
\color{black}
  \bitbox{3}{000}
  \bitbox{1}{0}
  \bitbox{2}{00}
\color{black}
  \bitbox{8}{nextA}
  \bitbox{8}{nextB}
\end{bytefield}}

The {\tt P} field is a predicate; if it does not hold, the instruction
is ignored.  Otherwise the two flags ({\tt A} and {\tt B}) are updated
according to the {\tt nextA} and {\tt nextB} fields; each specifies
the new value as the logical {\tt OR} of zero or more inputs:

\begin{center}
{\tt
\begin{bytefield}{8}
  \bitheader[b]{0-7}\\
  \bitbox{1}{${\text{\tt A}}$}
  \bitbox{1}{$\overline{\text{\tt A}}$}
  \bitbox{1}{${\text{\tt B}}$}
  \bitbox{1}{$\overline{\text{\tt B}}$}
  \bitbox{1}{${\text{\tt S}}$}
  \bitbox{1}{$\overline{\text{\tt S}}$}
  \bitbox{1}{${\text{\tt Z}}$}
  \bitbox{1}{$\overline{\text{\tt Z}}$}
\end{bytefield}}
\end{center}

Each bit corresponds to one possible input; all inputs whose bits are
set are {\tt OR}ed together, and the resulting value is assigned to
the flag.  Note that if none of the bits are set, the value assigned
is zero.  Note also that it is possible to produce a {\tt 1} by {\tt
  OR}ing any flag with its complement.


\pagebreak

\subsection{{\tt repeat}}

This instruction loads the repeat counter with either a literal
number, the special value $\infty$, or the contents of the {\tt data}
register.

\setlength{\bitwidth}{5mm}
{\tt
\begin{bytefield}{26}
  \bitheader[b]{16-19,21}\\
\color{light}
  \bitbox{1}{IM} 
  \bitbox{1}{DL} 
  \bitbox{2}{P}
\color{black}
  \bitbox{3}{000}
  \bitbox{1}{0}
  \bitbox{2}{01}
\color{light}
  \bitbox[tbr]{8}{}
  \bitbox[l]{8}{}
\color{black}
\end{bytefield}}\\

\begin{bytefield}{26}
  \bitbox[r]{18}{\raggedleft from data latch:\hspace{0.2cm}\ }
  \bitbox{2}{\tt 00}
\color{light}
  \bitbox[tbr]{6}{} 
\color{black}
\end{bytefield}

\begin{bytefield}{26}
  \bitheader[b]{0,5,6,7}\\
  \bitbox[r]{18}{\raggedleft from literal:\hspace{0.2cm}\ }
  \bitbox{2}{\tt 10}
  \bitbox{6}{\tt Literal} 
\end{bytefield}

\begin{bytefield}{26}
  \bitheader[b]{0,5,6,7}\\
  \bitbox[r]{18}{\raggedleft with $\infty$\ \ }
  \bitbox{2}{\tt 11} 
\color{light}
  \bitbox[tbr]{6}{} 
\color{black}
\end{bytefield}


\subsection{{\tt loop}}

This instruction loads the loop counter with either a literal or the
contents of the {\tt data} register.

\setlength{\bitwidth}{5mm}
{\tt
\begin{bytefield}{26}
  \bitheader[b]{16-19,21,24}\\
\color{light}
  \bitbox{1}{IM} 
\color{black}
  \bitbox{1}{0} 
\color{light}
  \bitbox[tbr]{2}{P}
\color{black}
  \bitbox{3}{000}
  \bitbox{1}{0}
  \bitbox{2}{10}
\color{light}
  \bitbox[tbr]{9}{} 
  \bitbox[l]{7}{}
\color{black}
\end{bytefield}}\\

\begin{bytefield}{26}
  \bitbox[r]{19}{\raggedleft from data latch:\hspace{0.2cm}\ }
  \bitbox{1}{\tt 0} 
\color{light}
  \bitbox[tbr]{6}{} 
\color{black}
\end{bytefield}

\begin{bytefield}{26}
  \bitheader[b]{0,5,6}\\
  \bitbox[r]{19}{\raggedleft from literal:\hspace{0.2cm}\ }
  \bitbox{1}{\tt 1} 
  \bitbox{6}{\tt Literal} 
\end{bytefield}

Note that the bit normally marked {\tt DL} (``decrement loop
      counter'') {\bf must} be set to {\tt
  0} in this case.

\pagebreak
\subsection{{\tt takeLoopCounter}}

\setlength{\bitwidth}{5mm}
{\tt
\begin{bytefield}{26}
  \bitheader[b]{16-19,21}\\
\color{light}
  \bitbox{1}{IM} 
  \bitbox{1}{DL} 
  \bitbox{2}{P}
\color{black}
  \bitbox{3}{000}
  \bitbox{1}{0}
  \bitbox{2}{11}
\color{light}
  \bitbox[tbr]{16}{} 
\color{black}
\end{bytefield}}

The {\tt P} field is a predicate; if it does not hold, the instruction
is ignored (but may reloop).  This instruction copies the value in the
loop counter {\tt LC} into the least significant bits of the data
latch and leaves all other bits of the data latch unchanged.

\subsection{{\tt takeRepeatCounter}}

\setlength{\bitwidth}{5mm}
{\tt
\begin{bytefield}{26}
  \bitheader[b]{16-19,21}\\
\color{light}
  \bitbox{1}{IM} 
  \bitbox{1}{DL} 
  \bitbox{2}{P}
\color{black}
  \bitbox{3}{???}
  \bitbox{1}{?}
  \bitbox{2}{??}
\color{light}
  \bitbox[tbr]{16}{} 
\color{black}
\end{bytefield}}

The {\tt P} field is a predicate; if it does not hold, the instruction
is ignored (but may reloop).  This instruction copies the value in the
repeat counter {\tt RC} into the least significant bits of the data
latch and leaves all other bits of the data latch unchanged.

\pagebreak
\subsection{{\tt interrupt}}

\setlength{\bitwidth}{5mm}
{\tt
\begin{bytefield}{26}
  \bitheader[b]{0,5,16-19,21}\\
\color{light}
  \bitbox{4}{} 
\color{black}
  \bitbox{3}{000} 
  \bitbox{1}{1}
  \bitbox{2}{00}
\color{light}
  \bitbox[tbr]{16}{} 
%\color{black}
%  \bitbox{6}{Count}
\end{bytefield}}

When an {\tt interrupt} instruction reaches {\tt IH}, it will wait
there for the {\tt OD} stage to be full with an instruction that has
the {\tt IM} bit set.  When this occurs, the instruction at {\tt OD}
{\it will not execute}, but {\it may reloop} if the conditions for
relooping are met.
\footnote{The ability to interrupt an instruction yet have it reloop is very
useful for processing chunks of data with a fixed size header and/or
footer and a variable length body.}


\subsection{{\tt massacre}}

\setlength{\bitwidth}{5mm}
{\tt
\begin{bytefield}{26}
  \bitheader[b]{16-19,21}\\
\color{light}
  \bitbox{4}{} 
\color{black}
  \bitbox{3}{000} 
  \bitbox{1}{1}
  \bitbox{2}{01}
\color{light}
  \bitbox[tbr]{16}{} 
\color{black}
\end{bytefield}}

When a {\tt massacre} instruction reaches {\tt IH}, it will wait there
for the {\tt OD} stage to be full with an instruction that has the
{\tt IM} bit set.  When this occurs, all instructions in the
instruction fifo (including {\tt OD}) are retired.

\subsection{{\tt clog}}

\setlength{\bitwidth}{5mm}
{\tt
\begin{bytefield}{26}
  \bitheader[b]{16-19,21}\\
\color{light}
  \bitbox{4}{} 
\color{black}
  \bitbox{3}{000} 
  \bitbox{1}{1}
  \bitbox{2}{10}
\color{light}
  \bitbox[tbr]{16}{} 
\color{black}
\end{bytefield}}

When a {\tt clog} instruction reaches {\tt OD}, it remains there and
no more instructions will be executed until an {\tt unclog} is
performed.

\subsection{{\tt unclog}}

\setlength{\bitwidth}{5mm}
{\tt
\begin{bytefield}{26}
  \bitheader[b]{16-19,21}\\
\color{light}
  \bitbox{4}{} 
\color{black}
  \bitbox{3}{000} 
  \bitbox{1}{1}
  \bitbox[lrtb]{2}{11}
\color{light}
  \bitbox[tbr]{16}{} 
\color{black}
\end{bytefield}}

When an {\tt unclog} instruction reaches {\tt IH}, it will wait there
until a {\tt clog} instruction is at {\tt OD}.  When this occurs, both
instructions retire.

Note that issuing an {\tt unclog} instruction to a dock which is not
clogged and whose instruction fifo contains no {\tt clog} instructions
will cause the dock to deadlock.



\pagebreak
\epsfig{file=overview,height=5in,angle=90}

\pagebreak
\epsfig{file=ports,height=5in,angle=90}

\pagebreak
\epsfig{file=best,height=5in,angle=90}


\end{document}
