HredFive|8.10k

# External Libraries:

LorangeTSMC090nm|orangeTSMC090nm

# Cell invCLK;1{sch}
CinvCLK;1{sch}||schematic|1021415734000|1158010267102||ATTR_Delay(D5G1;HNPX-12;Y-5.5;)I100|ATTR_X(D5FLeave alone;G1;HNOLPX-12;Y-4.5;)S1|ATTR_drive0(D5G1;HNPTX-12;Y-6.5;)Sstrong0|ATTR_drive1(D5G1;HNPTX-12;Y-7.5;)Sstrong1|ATTR_verilog_template(D5G1;NTX28.5;Y-15;)Snot ($(drive0), $(drive1)) #($(Delay)) $(node_name) ($(out), $(in));|prototype_center()I[0,0]
IorangeTSMC090nm:NMOSx;1{ic}|NMOS@0||0|-6|||D0G4;|ATTR_Delay(D5G1;NOJPX3.5;Y-2;)S@Delay|ATTR_X(D5FLeave alone;G1.5;NOLPX3.5;Y0.5;)S@X
IorangeTSMC090nm:PMOSx;1{ic}|PMOS@0||0|6|||D0G4;|ATTR_Delay(D5G1;NOJPX3.5;Y-2;)S@Delay|ATTR_X(D5FLeave alone;G1.5;NOLPX3.5;Y0.5;)S@X*1.5
Ngeneric:Facet-Center|art@0||0|0||||AV
NOff-Page|conn@0||8|0||||
NOff-Page|conn@1||-11|0||||
NGround|gnd@0||0|-12.5||||
IinvCLK;1{ic}|invCLK@0||16|10.5|||D0G4;|ATTR_Delay(D5G1;NPX2;Y-2;)I100|ATTR_X(D5FLeave alone;G1.5;NOLPX1.5;Y2;)S1|ATTR_drive0(P)Sstrong0|ATTR_drive1(P)Sstrong1
Ngeneric:Invisible-Pin|pin@0||-0.5|19|||||ART_message(D5G2;)S[intended for driving clock circuits - gives nearly equal rise/fall]
Ngeneric:Invisible-Pin|pin@1||-1|28|||||ART_message(D5G6;)S[invCLK]
Ngeneric:Invisible-Pin|pin@2||0|23|||||ART_message(D5G2;)S[medium HI-threshold fixed-size (non-LE) inverter]
NWire_Pin|pin@3||0|0||||
NWire_Pin|pin@4||-4|6||||
NWire_Pin|pin@5||-4|-6||||
NWire_Pin|pin@6||-4|0||||
Ngeneric:Invisible-Pin|pin@7||1|21|||||ART_message(D5G2;)S[P to N width ratio is 3 to 1]
Ngeneric:Invisible-Pin|pin@8||28|-10.5|||||ART_message(D5G2;)S[X is drive strength,P drive strength is twice N strength]
NPower|pwr@0||0|12.5||||
Awire|net@0|||0|conn@0|a|6|0|pin@3||0|0
Awire|net@1|||2700|pin@6||-4|0|pin@4||-4|6
Awire|net@2|||2700|pin@5||-4|-6|pin@6||-4|0
Awire|net@3|||0|pin@6||-4|0|conn@1|y|-9|0
Awire|net@4|||1800|pin@5||-4|-6|NMOS@0|g|-3|-6
Awire|net@5|||900|pin@3||0|0|NMOS@0|d|0|-4
Awire|net@6|||2700|gnd@0||0|-10.5|NMOS@0|s|0|-8
Awire|net@7|||2700|pin@3||0|0|PMOS@0|d|0|4
Awire|net@8|||1800|pin@4||-4|6|PMOS@0|g|-3|6
Awire|net@9|||900|pwr@0||0|12.5|PMOS@0|s|0|8
Ein||D5G2;|conn@1|a|I
Eout||D5G2;|conn@0|y|O
X