HregistersM|8.10k # External Libraries: LlatchesK|latchesK # Cell data2in60Cx18;1{sch} Cdata2in60Cx18;1{sch}||schematic|1189373179324|1230573926741|I Ngeneric:Facet-Center|art@0||0|0||||AV NOff-Page|conn@0||12|0|||| NOff-Page|conn@1||-14|-3|||| NOff-Page|conn@2||-8|-8.5|||YRRR| NOff-Page|conn@3||-14|3|||XRR| Idata2in60Cx18;1{ic}|hi2inAdd@0||15|8|||D5G4; IlatchesK:latch2in60C;1{ic}|hiL[1:18]|D5G3;X3;Y4;|0|0|||D5G4; Ngeneric:Invisible-Pin|pin@0||1|34|||||ART_message(D5G6;)Sdata2in60Cx18 Ngeneric:Invisible-Pin|pin@1||0|25|||||ART_message(D5G3;)Sies 29 December 2008 Ngeneric:Invisible-Pin|pin@2||-1|29|||||ART_message(D5G4;)SHI control data register NBus_Pin|pin@7||-8|1|-1|-1|| NBus_Pin|pin@8||-8|3|-1|-1|| NBus_Pin|pin@11||-8|-3|-1|-1|| NBus_Pin|pin@12||-8|-1|-1|-1|| NWire_Pin|pin@13||-2|-6|||| NWire_Pin|pin@14||-2|7|||| Ngeneric:Invisible-Pin|pin@15||-5.5|17|||||ART_message(D6G2;)S[Bit arrangement right:,18 17 16 15 14 13 12 11 10,01 02 03 04 05 06 07 08 09] Ngeneric:Invisible-Pin|pin@16||-8.5|17|||||ART_message(D4G2;)S[Bit arrangement left:,10 11 12 13 14 15 16 17 18,09 08 07 06 05 04 03 02 01] Awire|dcl[A]|D5G2;||900|hiL[1:18]|hcl[A]|-2|-3|pin@13||-2|-6 Awire|dcl[B]|D5G2;||2700|hiL[1:18]|hcl[B]|-2|3|pin@14||-2|7 Abus|net@9||-0.5|IJ0|conn@0|a|10|0|hiL[1:18]|out[1]|3|0 Abus|net@10||-0.5|IJ0|hiL[1:18]|inB[1]|-3|1|pin@7||-8|1 Abus|net@11||-0.5|IJ2700|pin@7||-8|1|pin@8||-8|3 Abus|net@15||-0.5|IJ1800|conn@1|y|-12|-3|pin@11||-8|-3 Abus|net@16||-0.5|IJ2700|pin@11||-8|-3|pin@12||-8|-1 Abus|net@17||-0.5|IJ1800|pin@12||-8|-1|hiL[1:18]|inA[1]|-3|-1 Abus|net@19||-0.5|IJ1800|conn@3|y|-12|3|pin@8||-8|3 Edcl[A,B]||D4G2;|conn@2|a|I EinA[1:18]||D4G2;|conn@1|a|I EinB[1:18]||D4G2;|conn@3|a|I Eout[1:18]||D6G2;|conn@0|y|O X