HredFive|8.10k

# Cell nand3LT_sy6;1{sch}
Cnand3LT_sy6;1{sch}||schematic|1021415734000|1248729055117||ATTR_Delay(D5G1;HNPX-30;Y-12.5;)I100|ATTR_X(D5G1;HNPX-30;Y-11.5;)I1|ATTR_drive0(D5G1;HNPTX-30;Y-13.5;)Sstrong0|ATTR_drive1(D5G1;HNPTX-30;Y-14.5;)Sstrong1|ATTR_verilog_template(D5G1;NTX19;Y-24;)Snand ($(drive0), $(drive1)) #($(Delay)) $(node_name) ($(out), $(ina), $(inb), $(inc));|prototype_center()I[0,0]
IPMOS;1{ic}|PMOS@3||-14|4|||D0G4;|ATTR_Delay(D5G1;NOJPX3.5;Y-2;)S@Delay|ATTR_X(D5G1.5;NOJPX3.5;Y0.5;)S@X/3.
IPMOS;1{ic}|PMOS@4||-5|4|||D0G4;|ATTR_Delay(D5G1;NOJPX3.5;Y-2;)S@Delay|ATTR_X(D5G1.5;NOJPX3.5;Y0.5;)S@X/3.
IPMOS;1{ic}|PMOS@5||4.5|4|YRR||D0G4;|ATTR_Delay(D5G1;NOJPX3.5;Y-2;)S@Delay|ATTR_X(D5G1.5;NOJPX3.5;Y0.5;)S@X/3.
Ngeneric:Facet-Center|art@0||0|0||||AV
NOff-Page|conn@1||24|-12.5|||RR|
NOff-Page|conn@2||27|0||||
NOff-Page|conn@3||-35|4||||
NOff-Page|conn@4||-35|-2.5||||
Inand3LT_sy6;1{ic}|nand3LT_@0||35|19.5|||D0G4;|ATTR_Delay(D5G1;NPX4;Y-2.5;)I100|ATTR_X(D5G1.5;NPX3;Y2.5;)I1|ATTR_drive0(P)Sstrong0|ATTR_drive1(P)Sstrong1|ATTR_LEGATE()I1|ATTR_su()I-1
Inms3_sy6;1{ic}|nms3_sy3@0||-10|-16.5|||D0G4;|ATTR_Delay(D5G1;NOJPX-8.5;Y-1.5;)S@Delay|ATTR_X(D5G1.5;NOJPX-8.5;Y2;)S@X
NWire_Pin|pin@10||-19.5|-8.5||||
NWire_Pin|pin@11||-21.5|-16.5||||
NWire_Pin|pin@12||10.5|-12.5||||
NWire_Pin|pin@13||-19.5|4||||
NWire_Pin|pin@14||-21.5|-2.5||||
NWire_Pin|pin@15||-9|-2.5||||
NWire_Pin|pin@16||-5|7.5||||
NWire_Pin|pin@17||4.5|7.5||||
NWire_Pin|pin@18||-14|7.5||||
Ngeneric:Invisible-Pin|pin@19||0|16.5|||||ART_message(D5G2;)S[Sized assuming that all 3 inputs go low together]
Ngeneric:Invisible-Pin|pin@20||28.5|-19|||||ART_message(D5G2;)S[X is drive strength,Three pull-ups have the same strength,as the pull-down]
Ngeneric:Invisible-Pin|pin@21||-0.5|18|||||ART_message(D5G2;)S[P to N width ratio is 2/3 to 3]
NWire_Pin|pin@22||-9|4||||
NWire_Pin|pin@23||-5|0||||
Ngeneric:Invisible-Pin|pin@24||-0.5|20|||||ART_message(D5G2;)S[one-parameter NAND]
NWire_Pin|pin@25||4.5|0||||
NWire_Pin|pin@26||10.5|4||||
Ngeneric:Invisible-Pin|pin@27||-0.5|25|||||ART_message(D5G6;)Snand3LT_sy6
NWire_Pin|pin@28||-14|0||||
NPower|pwr@0||-5|10.5||||
Awire|net@16|||0|pin@25||4.5|0|pin@23||-5|0
Awire|net@25|||1800|pin@10||-19.5|-8.5|nms3_sy3@0|g3|-7.5|-8.5
Awire|net@26|||2700|pin@10||-19.5|-8.5|pin@13||-19.5|4
Awire|net@27|||1800|pin@11||-21.5|-16.5|nms3_sy3@0|g|-7.5|-16.5
Awire|net@28|||2700|pin@11||-21.5|-16.5|pin@14||-21.5|-2.5
Awire|net@29|||0|pin@12||10.5|-12.5|nms3_sy3@0|g2|-2.5|-12.5
Awire|net@30|||900|pin@26||10.5|4|pin@12||10.5|-12.5
Awire|net@31|||900|pin@23||-5|0|nms3_sy3@0|d|-5|-5.5
Awire|net@32|||2700|PMOS@3|s|-14|6|pin@18||-14|7.5
Awire|net@33|||0|PMOS@3|g|-17|4|pin@13||-19.5|4
Awire|net@34|||900|PMOS@3|d|-14|2|pin@28||-14|0
Awire|net@35|||2700|PMOS@4|s|-5|6|pin@16||-5|7.5
Awire|net@36|||0|PMOS@4|g|-8|4|pin@22||-9|4
Awire|net@37|||900|PMOS@4|d|-5|2|pin@23||-5|0
Awire|net@38|||900|pin@17||4.5|7.5|PMOS@5|s|4.5|6
Awire|net@39|||1800|PMOS@5|g|7.5|4|pin@26||10.5|4
Awire|net@40|||900|PMOS@5|d|4.5|2|pin@25||4.5|0
Awire|net@41|||1800|pin@14||-21.5|-2.5|pin@15||-9|-2.5
Awire|net@42|||900|pin@22||-9|4|pin@15||-9|-2.5
Awire|net@43|||900|pwr@0||-5|10.5|pin@16||-5|7.5
Awire|net@44|||1800|pin@16||-5|7.5|pin@17||4.5|7.5
Awire|net@45|||1800|pin@18||-14|7.5|pin@16||-5|7.5
Awire|net@46|||1800|pin@28||-14|0|pin@23||-5|0
Awire|net@47|||1800|pin@25||4.5|0|conn@2|a|25|0
Awire|net@48|||1800|pin@12||10.5|-12.5|conn@1|y|22|-12.5
Awire|net@49|||1800|conn@3|y|-33|4|pin@13||-19.5|4
Awire|net@50|||1800|conn@4|y|-33|-2.5|pin@14||-21.5|-2.5
Eina||D5G2;|conn@4|y|I
Einb||D5G2;|conn@1|a|I
Einc||D5G2;|conn@3|y|I
Eout||D5G2;|conn@2|y|O
X