* Self loaded min geometry inverter, sample HSPICE file

* Include the model files

* Include the hspice model files for 0.18u technology. 

******************************************************************
* Set Process, Voltage and Temperature corner
******************************************************************

.protect

* 90nm
*.lib '/import/async/cad/process/tsmc090/spice_models/models/cln90g_lk.l' TT
*.lib '/import/async/cad/process/tsmc090/spice_models/models/cln90g_lk.l' TT_RES
*.lib '/import/async/cad/process/tsmc090/spice_models/models/cln90g_lk.l' TT_18
*.lib '/import/async/cad/process/tsmc090/spice_models/models/cln90g_lk.l' TT_na18
*.lib '/import/async/cad/process/tsmc090/spice_models/models/cln90g_lk.l' TT_DIO_esd
*.lib '/import/async/cad/process/tsmc090/spice_models/models/cln90g_lk.l' TT_DIO_18

* 40nm
.lib '/import/async/cad/process/tsmcsun045/sun_spice_models/1.01/models/toplevel_cln40gp.l' TOP_TT

.unprotect


.param sup=0.9    * Supply voltage
.temp 80          * Temperature

******************************************************************
* Standard Parameters and Options
******************************************************************

.param vsupply=sup
.param vhi=sup
.param vlo=0
.param strong0=0 * Used in verilog, just needs to be defined to run hspice
.param strong1=1 * Used in verilog, just needs to be defined to run hspice

.options ACCT OPTS post
*.option post probe
* .opt scale=0.05u
.op

.param AVT0N = AGAUSS(0.0,  '0.01 / 0.1' , 1)
.param AVT0P = AGAUSS(0.0,  '0.01 / 0.1' , 1)
.param ABN = AGAUSS(0.0,  '0.02 / 0.1' , 1)
.param ABP = AGAUSS(0.0,  '0.02 / 0.1' , 1)

.post=3

.include 'omegaCounter.spi'

.tran 1n 400n

.end