#include "contrib/demo.ships"

// values and addresses to write
1: sendto mem.write_addr;
2: sendto mem.write_addr;
3: sendto mem.write_addr;
9: sendto mem.write_data;
8: sendto mem.write_data;
7: sendto mem.write_data;

// memory write ports accept the values
mem.write_addr:  [*] take, deliver;
mem.write_data:  [*] take, deliver;

// once all three are written, cue the fifo
mem.write_done:
  [3] take;
  ack fifo.out;

// meanwhile, the fifo is sitting on a set of read addresses
fifo.in: [*] take, deliver;
1: sendto fifo.in;
2: sendto fifo.in;
3: sendto fifo.in;
1: sendto fifo.in;
1: sendto fifo.in;
1: sendto fifo.in;

// when it gets the ack, it issues them all to the memory read unit
fifo.out:
  wait;
  [*] take, sendto mem.read_addr;

// values read from memory go to debug (which accepts them)
mem.read_addr:   [*] take, deliver;
mem.read_data:   [*] take, sendto debug.data;
debug.data:      [*] take, deliver;