\documentclass[10pt]{book}
\usepackage{amsmath}
\usepackage{palatino}
\usepackage{parskip}
\usepackage{register}
\usepackage{bytefield}
\renewcommand{\ttdefault}{cmtt}
\title{The FleetTwo Architecture Manual}
\begin{document}
\maketitle

\pagebreak
\section*{Data Formats}

\subsection*{Packet Destination Address (12 bits)}

These bits appear physically within the switch fabric, and have
``address bit timing.''  The {\tt T} bit is the ``tokenhood'' bit; if
set, this packet represents a token and it does not cause the switch
fabric data latches to fire.

{\tt\footnotesize
\begin{bytefield}{49}
  \bitheader[b]{37,47,48}\\
  \bitbox{1}{T} 
  \bitbox{11}{Destination Address} 
  \bitbox[l]{37}{} 
\end{bytefield}
}

\subsection*{Data Word In Memory (37 bits)}

A word of memory is 37 bits wide.  For convenience, we assume that the
memory word width is also the width of a pointer as well as the width
of all on-chip data item registers.

{\tt\footnotesize
\begin{bytefield}{49}
  \bitheader[b]{0,36}\\
  \bitbox[r]{12}{}
  \bitbox{37}{Data Word} 
\end{bytefield}
}

\subsection*{Data Packet In Flight (49 bits)}

A {\it data packet} is a data item in the switch fabric, on its way to
some destination.

{\tt\footnotesize
\begin{bytefield}{49}
  \bitheader[b]{0,36,37,47,48}\\
  \bitbox{1}{T} 
  \bitbox{11}{Destination Address} 
  \bitbox{37}{Data Word} 
\end{bytefield}
}

\subsection*{Instruction In Memory (37 bits)}

An instruction must be no wider than a memory word.  The next section
explains the bits in greater detail.

{\tt\tiny
\begin{bytefield}{49}
  \bitheader[b]{0,10,11,17,18-26,36}\\
  \bitbox[r]{12}{}
  \bitbox{11}{Instruction Register Address} 
  \bitbox{1}{K} 
  \bitbox{1}{L} 
  \bitbox{1}{Ti} 
  \bitbox{1}{Di} 
  \bitbox{1}{Ld} 
  \bitbox{1}{Do} 
  \bitbox{1}{To} 
  \bitbox{1}{Rq} 
  \bitbox{7}{Count} 
  \bitbox{11}{Data/Token Destination} 
\end{bytefield}
}

\subsection*{Instruction Packet In Flight (49 bits)}

A {\it instruction packet} is an instruction in the instruction horn
(which may or may not be the same thing as the data horn), on its way
to some instruction register (BenkoBox).

{\tt\tiny
\begin{bytefield}{49}
  \bitheader[b]{0,10,11,17,18-25,37,47,48}\\
  \bitbox[r]{1}{0} 
  \bitbox{11}{Instruction Register Address} 
  \bitbox[lr]{11}{}
  \bitbox{1}{K} 
  \bitbox{1}{L} 
  \bitbox{1}{Ti} 
  \bitbox{1}{Di} 
  \bitbox{1}{Ld} 
  \bitbox{1}{Do} 
  \bitbox{1}{To} 
  \bitbox{1}{Rq} 
  \bitbox{7}{Count} 
  \bitbox{11}{Data/Token Destination} 
\end{bytefield}
}


\pagebreak

\section*{Instruction Format Detail}

\setlength{\bitwidth}{5mm}
{\tt
\begin{bytefield}{26}
  \bitheader[b]{0,10,11,17,18-25}\\
  \bitbox{1}{K} 
  \bitbox{1}{L} 
  \bitbox{1}{Ti} 
  \bitbox{1}{Di} 
  \bitbox{1}{Ld} 
  \bitbox{1}{Do} 
  \bitbox{1}{To} 
  \bitbox{1}{Rq} 
  \bitbox{7}{C} 
  \bitbox{11}{Dest} 
\end{bytefield}
}

\begin{itemize}

   \item [\tt K] ({\bf Kill}) if set, this instruction is a kill;
                 ignore all further directions below.

   \item [\tt L] ({\bf Literal}) if set, use all bits below except
                 {\tt Count} (17 bits) as a literal, sign extend them,
                 and load into the data register; ignore all further
                 directions below except {\tt Count}.

  \item [\tt Ti] ({\bf Token Input}) wait for a token and acknowledge
                 it; {\tt Ti}=1,{\tt Di}=1 is invalid on inbox

  \item [\tt Di] ({\bf Data Input}) wait for a datum and acknowledge
                 it

  \item [\tt Dc] ({\bf Data Capture}) capture (latch) a datum; {\tt
                 Di}=0,{\tt Dc}=1 is invalid.  This bit is ignored if
                 the {\tt T} (token) bit is set on the incoming
                 packet.

  \item [\tt Do] ({\bf Data Output}) emit a datum

  \item [\tt To] ({\bf Token Output}) emit a token; {\tt To}=1,{\tt
                 Do}=1 is invalid on outbox

%  \item [\tt Fi] ({\bf Final Iteration}) emit a token when {\tt
%                 Count=0} (ie the last iteration of a requeueing
%                 loop); {\tt Tl}=1,{\tt To}=1 is invalid.

  \item [\tt Rq] ({\bf ReQueue}) if set, instructions having nonzero
                 count are ``Re-Queued'' in the instruction queue
                 after execution (see below); otherwise instructions
                 with nonzero count are executed again immediately.

  \item  [\tt C] ({\bf Count}) {\it After} executing:
\begin{verbatim}
if Count==0 { discard this instruction }
else {
    if Count<1111111 { decrement count }
    if Rq=1 and L=0 {
       put this instruction back into the instruction fifo
    } else {
       execute this instruction again
    }
}
\end{verbatim}               

\item [\tt Dest] ({\bf Data/Token Destination})
   Any packets (token or datum) emitted {\it to the switch fabric}
   will be emitted with this address in the packet's destination
   field.
\end{itemize}

\subsection*{Notes}
\begin{itemize}
\item A "standing" instruction is encoded as {\tt Count}=$\text{\tt 1111111}_\text{two}$

\item A {\tt clog} is encoded as a "standing" {\tt nop} ({\tt Ti},
      {\tt Di}, {\tt Dc}, {\tt Do}, {\tt To} all cleared)

\item An {\tt unclog} is encoded as {\tt K=1},{\tt Ti=1}

\end{itemize}
