# header information:
HtinyCounter|8.08k

# Views:
Vicon|ic
Vschematic|sch

# External Libraries:

LcentersJ|centersJ

LdriversM|driversM

LorangeTSMC090nm|orangeTSMC090nm

LredFive|redFive

# Tools:
Ouser|DefaultTechnology()Scmos90|SchematicTechnology()Scmos90
Oio|GDSOutputConvertsBracketsInExports()BF|GDSWritesExportPins()BT

# Technologies:
Tcmos90|"GDS(ST)LayerForPad-FrameINcmos90"()S43|"GDS(TSMC)LayerForPad-FrameINcmos90"()S43
Tmocmos|SelectedFoundryFormocmos()STSMC

# Cell counterTopLevel;1{sch}
CcounterTopLevel;1{sch}||schematic|1246318914852|1246318917028|
Ngeneric:Facet-Center|art@0||0|0||||AV
Ngeneric:Invisible-Pin|pin@0||-5|9.5|||||ART_message(D5G3;)S["A complete counter consists of \"n\" copies of this cell","plus an \"end cap\" at the MSB end and a different \"end cap\" at the LSB end.",.,The MSB end cap ties DoneOrTwo HI and OneOrTwo LO.,.,The LSB end cap responds to decrement requests from the,"dock by draining both state wires.  It reports \"decrement succeeded\" to","the dock if the state of the LSB is \"One\" or \"Two\" and reports \"decrement","failed\" to the dock if the state of the LSB is \"Done\"."]
X

# Cell nor2withInverter;2{ic}
Cnor2withInverter;2{ic}||artwork|1021415734000|1246318194856|E|ATTR_Delay(D5G1;HNPX-2.5;Y5.5;)I100|ATTR_X(D5FLeave alone;G1;HNOLPX-2.5;Y6.5;)S1|ATTR_drive0(D5G1;HNPTX-2.5;Y4.5;)Sstrong0|ATTR_drive1(D5G1;HNPTX-2.5;Y3.5;)Sstrong1|prototype_center()I[6000,0]
Ngeneric:Facet-Center|art@0||0|0||||AV
NThick-Circle|art@1||-1|1|1|1|||ART_color()I10
NThick-Circle|art@2||0.5|0|4|4|RRR||ART_color()I10|ART_degrees()F[0.0,3.1415927]
NThick-Circle|art@4||-3|-1|1|1|||ART_color()I10
NPin|pin@0||-0.5|-0.75|1|1||
NPin|pin@1||0.75|-2|1|1||
NPin|pin@2||0.5|-2|1|1||
NPin|pin@3||-0.5|-2|1|1||
NPin|pin@4||-0.5|2|1|1||
NPin|pin@5||0.5|2|1|1||
NPin|pin@6||-1.5|1|1|1||
NPin|pin@7||-2.5|1||||
Nschematic:Bus_Pin|pin@8||3.5|0|-2|-2||
Nschematic:Bus_Pin|pin@9||-2.5|1|-2|-2||
Nschematic:Bus_Pin|pin@12||-7|-1|-2|-2||
NPin|pin@13||-3.5|-1|1|1||
Nschematic:Bus_Pin|pin@14||-7|-1|-2|-2||
NPin|pin@15||-6|-1|1|1||
NPin|pin@16||-7|-1||||
Nschematic:Bus_Pin|pin@17||-2.5|-1|-2|-2||
NPin|pin@18||-6|0.5|1|1||
NPin|pin@19||-6|-2.5|1|1||
NPin|pin@20||-2.5|-1|1|1||
NPin|pin@21||-0.5|-1|1|1||
NPin|pin@22||-1.5|-3|1|1|R|
NPin|pin@23||-1.5|-1|1|1|R|
Nschematic:Wire_Pin|pin@24||-1.5|-3||||
NPin|pin@25||3.5|0|1|1||
NPin|pin@26||2.5|0||||
AThicker|net@0|||FS3150|pin@1||0.75|-2|pin@0||-0.5|-0.75|ART_color()I10
AThicker|net@1|||FS0|pin@2||0.5|-2|pin@3||-0.5|-2|ART_color()I10
AThicker|net@2|||FS2700|pin@3||-0.5|-2|pin@4||-0.5|2|ART_color()I10
AThicker|net@3|||FS0|pin@5||0.5|2|pin@4||-0.5|2|ART_color()I10
AThicker|net@4|||FS0|pin@6||-1.5|1|pin@7||-2.5|1|ART_color()I10
AThicker|net@6|||FS3290|pin@13||-3.5|-1|pin@18||-6|0.5|ART_color()I10
AThicker|net@7|||FS310|pin@13||-3.5|-1|pin@19||-6|-2.5|ART_color()I10
AThicker|net@8|||FS0|pin@15||-6|-1|pin@16||-7|-1|ART_color()I10
AThicker|net@9|||FS2700|pin@19||-6|-2.5|pin@18||-6|0.5|ART_color()I10
AThicker|net@10|||FS1800|pin@20||-2.5|-1|pin@21||-0.5|-1|ART_color()I-16777215
AThicker|net@11|||FS2700|pin@22||-1.5|-3|pin@23||-1.5|-1|ART_color()I-16777215
AThicker|net@12|||FS0|pin@25||3.5|0|pin@26||2.5|0|ART_color()I10
Eina||D5G1;X1.5;|pin@12||I
Einb||D5G1;|pin@9||I
Eout||D5G1;|pin@8||O
EoutaBar||D5G1;Y-0.5;|pin@24||U
X

# Cell nor2withInverter;1{sch}
Cnor2withInverter;1{sch}||schematic|1021415734000|1246318014836||ATTR_Delay(D5G1;HNPX-18;Y-6;)I100|ATTR_X(D5FLeave alone;G1;HNOLPX-18;Y-5;)S1|ATTR_drive0(D5G1;HNPTX-18;Y-7;)Sstrong0|ATTR_drive1(D5G1;HNPTX-18;Y-8;)Sstrong1|ATTR_verilog_template(D5G1;NTX5.5;Y-18.5;)SFIXME!!! nor ($(drive0), $(drive1)) #($(Delay)) $(node_name) ($(out), $(ina), $(inb));|prototype_center()I[0,0]
IorangeTSMC090nm:NMOSx;1{ic}|NMOS@0||-4|-8|||D0G4;|ATTR_Delay(D5G1;NOJPX3.5;Y-2;)S@Delay|ATTR_X(D5FLeave alone;G1.5;NOLPX3.5;Y0.5;)S@X
IorangeTSMC090nm:NMOSx;1{ic}|NMOS@1||4|-8|YRR||D0G4;|ATTR_Delay(D5G1;NOJPX3.5;Y-2;)S@Delay|ATTR_X(D5FLeave alone;G1.5;NOLPX3.5;Y0.5;)S@X
IorangeTSMC090nm:NMOSx;1{ic}|NMOSx@0||-3|11.5|Y||D0G4;|ATTR_Delay(D5G1;NOJPX3.5;Y-2;)S@Delay|ATTR_X(D5FLeave alone;G1.5;NOLPX3.5;Y0.5;)S@X
IredFive:PMOS;1{ic}|PMOS@0||0|20.5|||D5G4;|ATTR_Delay(D5G1;NPX5;Y-2;)I100|ATTR_X(D5G1.5;NPX5;Y0.5;)I1
IredFive:PMOS;1{ic}|PMOS@1||0|4|RR||D5G4;|ATTR_Delay(D5G1;NPX5;Y-2;)I100|ATTR_X(D5G1.5;NPX5;Y0.5;)I1
Ngeneric:Facet-Center|art@0||0|0||||AV
NOff-Page|conn@0||-15.5|0||||
NOff-Page|conn@1||14|-8|||RR|
NOff-Page|conn@2||14|0||||
NOff-Page|conn@3||14|15||||
NGround|gnd@0||0|-15||||
NGround|gnd@1||-3|5.5||||
Inor2withInverter;2{ic}|nor2with@0||33.5|16|||D5G4;|ATTR_Delay(D5G1;NPX-5.25;Y-4;)I100|ATTR_X(D5FLeave alone;G1;NOLPX-5.25;Y-3;)S1|ATTR_drive0(P)Sstrong0|ATTR_drive1(P)Sstrong1
NWire_Pin|pin@0||0|-11.5||||
NWire_Pin|pin@1||-4|-11.5||||
NWire_Pin|pin@2||4|-11.5||||
NWire_Pin|pin@3||-9|-8||||
NWire_Pin|pin@5||-9|0||||
NWire_Pin|pin@6||9|4||||
NWire_Pin|pin@7||9|-8||||
Ngeneric:Invisible-Pin|pin@8||3|28.5|||||ART_message(D5G6;)Snor2withInverters
NWire_Pin|pin@9||-9|20.5||||
NWire_Pin|pin@10||0|0||||
NWire_Pin|pin@11||4|0||||
NWire_Pin|pin@12||-4|0||||
Ngeneric:Invisible-Pin|pin@13||27|-14|||||ART_message(D5G2;)S[X is drive strength,One pull-down is as strong,as the pull-up]
NWire_Pin|pin@14||-3|20.5||||
NWire_Pin|pin@15||3|4||||
NWire_Pin|pin@16||0|2||||
NWire_Pin|pin@17||-9|11.5||||
NWire_Pin|pin@18||-3|15||||
NWire_Pin|pin@19||0|15||||
NPower|pwr@0||0|25||||
Awire|net@0|||0|pin@7||9|-8|NMOS@1|g|7|-8
Awire|net@1|||900|pin@0||0|-11.5|gnd@0||0|-13
Awire|net@2|||0|pin@2||4|-11.5|pin@0||0|-11.5
Awire|net@3|||0|pin@0||0|-11.5|pin@1||-4|-11.5
Awire|net@4|||900|NMOS@0|s|-4|-10|pin@1||-4|-11.5
Awire|net@5|||2700|pin@2||4|-11.5|NMOS@1|s|4|-10
Awire|net@6|||900|pin@12||-4|0|NMOS@0|d|-4|-6
Awire|net@7|||0|NMOS@0|g|-7|-8|pin@3||-9|-8
Awire|net@8|||900|pin@11||4|0|NMOS@1|d|4|-6
Awire|net@9|||2700|pin@3||-9|-8|pin@5||-9|0
Awire|net@10|||0|pin@5||-9|0|conn@0|y|-13.5|0
Awire|net@11|||2700|pin@7||9|-8|pin@6||9|4
Awire|net@12|||1800|pin@7||9|-8|conn@1|y|12|-8
Awire|net@16|||0|pin@11||4|0|pin@10||0|0
Awire|net@17|||0|pin@10||0|0|pin@12||-4|0
Awire|net@18|||2700|pin@5||-9|0|pin@17||-9|11.5
Awire|net@19|||1800|pin@11||4|0|conn@2|a|12|0
Awire|net@20|||1800|pin@9||-9|20.5|pin@14||-3|20.5
Awire|net@21|||0|pin@6||9|4|pin@15||3|4
Awire|net@22|||2700|pin@10||0|0|pin@16||0|2
Awire|net@23|||0|PMOS@0|g|-3|20.5|pin@14||-3|20.5
Awire|net@24|||900|pwr@0||0|25|PMOS@0|s|0|22.5
Awire|net@25|||2700|PMOS@1|s|0|2|pin@16||0|2
Awire|net@26|||1800|PMOS@1|g|3|4|pin@15||3|4
Awire|net@27|||2700|PMOS@1|d|0|6|pin@19||0|15
Awire|net@28|||2700|pin@17||-9|11.5|pin@9||-9|20.5
Awire|net@29|||0|NMOSx@0|g|-6|11.5|pin@17||-9|11.5
Awire|net@30|||2700|NMOSx@0|s|-3|13.5|pin@18||-3|15
Awire|net@31|||2700|pin@19||0|15|PMOS@0|d|0|18.5
Awire|net@32|||1800|pin@18||-3|15|pin@19||0|15
Awire|net@33|||0|conn@3|a|12|15|pin@19||0|15
Awire|net@34|||2700|gnd@1||-3|7.5|NMOSx@0|d|-3|9.5
Eina||D5G2;|conn@0|a|I
Einb||D5G2;|conn@1|a|I
Eout||D5G2;|conn@2|y|O
EoutaBar||D5G2;X7.5;|conn@3|a|U
X

# Cell oneBit;1{ic}
ConeBit;1{ic}||artwork|1242937501096|1246320313399|E
Ngeneric:Facet-Center|art@0||0|0||||AV
NTriangle|art@2||-5|2|3|2|RRR|
NTriangle|art@3||3|-8|3|2|R|
NTriangle|art@4||3|2|3|2|R|
NPin|pin@0||-6|4|1|1||
NPin|pin@1||-6|-10|1|1||
NPin|pin@2||4|-10|1|1||
NPin|pin@3||4|4|1|1||
Nschematic:Wire_Pin|pin@9||-6|2||||
Nschematic:Wire_Pin|pin@16||4|2||||
Nschematic:Wire_Pin|pin@17||4|-8||||
Nschematic:Wire_Pin|pin@18||-6|-8||||
Nschematic:Wire_Pin|pin@19||-1|-10||||
NPin|pin@20||-6|-8|1|1||
Nschematic:Bus_Pin|pin@21||-6|-3||||
Nschematic:Wire_Pin|pin@22||-4|-3||||
Nschematic:Bus_Pin|pin@23||5|-7||||
Nschematic:Wire_Pin|pin@24||3|-7||||
Nschematic:Bus_Pin|pin@25||6|-6||||
Nschematic:Wire_Pin|pin@26||4|-6||||
Nschematic:Bus_Pin|pin@27||7|-8||||
Nschematic:Wire_Pin|pin@28||5|-8||||
ASolid|net@0|||FS900|pin@0||-6|4|pin@1||-6|-10
ASolid|net@1|||FS1800|pin@1||-6|-10|pin@2||4|-10
ASolid|net@2|||FS2700|pin@2||4|-10|pin@3||4|4
ASolid|net@3|||FS0|pin@3||4|4|pin@0||-6|4
Aschematic:wire|net@4|||0|pin@22||-4|-3|pin@21||-6|-3
Aschematic:wire|net@5|||1800|pin@24||3|-7|pin@23||5|-7
Aschematic:wire|net@6|||1800|pin@26||4|-6|pin@25||6|-6
Aschematic:wire|net@7|||1800|pin@28||5|-8|pin@27||7|-8
Eload||D5G2;|pin@27||U
EloadBar||D5G2;|pin@25||U
EloadVal|loadValBar|D5G2;|pin@23||U
Eload_or_master_clear||D5G2;|pin@21||U
Emc||D5G1;Y-1;|pin@19||I
Epred[TwoOrEmpty]|pred[DoneOrTwo]|D4G1;X-1;|pin@9||B
Epred[OneOrTwo]||D4G1;X-1;|pin@18||B
Esucc[TwoOrEmpty]|succ[DoneOrTwo]|D6G1;X1;|pin@16||B
Esucc[OneOrTwo]||D5G1;X2;|pin@17||B
X

# Cell oneBit;1{sch}
ConeBit;1{sch}||schematic|1242942044308|1246321007881|
IredFive:NMOS;1{ic}|NMOS@1||68.5|31|RR||D5G4;|ATTR_Delay(D5G1;NPX5;Y-2;)I100|ATTR_X(D5G1.5;NPX5;Y0.5;)I1
IredFive:NMOS;1{ic}|NMOS@2||68.5|25.5|RR||D5G4;|ATTR_Delay(D5G1;NPX5;Y-2;)I100|ATTR_X(D5G1.5;NPX5;Y0.5;)I1
IredFive:PMOS;1{ic}|PMOS@0||68.5|38|RR||D5G4;|ATTR_Delay(D5G1;NPX5;Y-2;)I100|ATTR_X(D5G1.5;NPX5;Y0.5;)I1
IredFive:PMOS;1{ic}|PMOS@1||68.5|43|RR||D5G4;|ATTR_Delay(D5G1;NPX5;Y-2;)I100|ATTR_X(D5G1.5;NPX5;Y0.5;)I1
Ngeneric:Facet-Center|art@0||0|0||||AV
NOff-Page|conn@0||33.5|3||||
NOff-Page|conn@1||-48|1|||RR|
NOff-Page|conn@2||-48|69||||
NOff-Page|conn@3||34|68||||
NOff-Page|conn@6||-48|76||||
NOff-Page|conn@7||82|34.5|||RR|
NOff-Page|conn@8||82|43|||RR|
NOff-Page|conn@9||82|25.5|||RR|
IcentersJ:ctrAND4in30;2{ic}|ctrAND4i@0||-1.5|58.5|R||D5G4;
NGround|gnd@0||68.5|21||||
Inor2withInverter;2{ic}|nor2with@0||-13.5|35.5|||D5G4;|ATTR_drive0(P)Sstrong0|ATTR_drive1(P)Sstrong1
Ngeneric:Invisible-Pin|pin@6||-74|129.5|||||ART_message(D5G15;)SoneBit
NWire_Pin|pin@115||-42|1||||
NWire_Pin|pin@120||-40.5|69||||
NWire_Pin|pin@127||29|34.5||||
NWire_Pin|pin@128||29|3||||
NWire_Pin|pin@129||29|68||||
NWire_Pin|pin@130||29|36.5||||
Ngeneric:Invisible-Pin|pin@149||-74.5|119|||||ART_message(D5G2;)Sam 29 Jun 2009
Ngeneric:Invisible-Pin|pin@162||-10.5|110.5|||||ART_message(D5G3;)S[Each bit of the counter has four states:,"Zero, One, Two, Done",.,These states are encoded by two state wires:,"DoneOrTwo is HI if the state is \"Done\" or \"Two\"","OneOrTwo is HI if the state is \"One\" or \"Two\""]
NWire_Pin|pin@163||5|68||||
NWire_Pin|pin@165||18.5|36.5||||
NWire_Pin|pin@167||18|34.5||||
NWire_Pin|pin@178||-3.5|35.5||||
NWire_Pin|pin@179||-40.5|34.5||||
NWire_Pin|pin@180||-42|36.5||||
NWire_Pin|pin@181||0.5|34.5||||
NWire_Pin|pin@182||2.5|36.5||||
Ngeneric:Invisible-Pin|pin@194||-69|55|||||ART_message(D5G4;)SMSB to the Left
Ngeneric:Invisible-Pin|pin@195||53|53.5|||||ART_message(D5G4;)SLSB to the Right
Ngeneric:Invisible-Pin|pin@196||-73.5|121.5|||||ART_message(D5G2;)S"this GasP module sits \"between\" two bits"
NWire_Pin|pin@206||-5.5|48.5||||
NWire_Pin|pin@214||-5|35.5||||
NWire_Pin|pin@218||-15|28.5||||
NWire_Pin|pin@219||-23|28.5||||
NWire_Pin|pin@220||-23|4||||
NWire_Pin|pin@224||-7|28.5||||
NWire_Pin|pin@225||-7|4||||
Ngeneric:Invisible-Pin|pin@226||-78|91|||||ART_message(D6FMonospaced;G3;)S[Ye Olde Firing Rules:,* Fire when there is a non-Zero on the left and a Zero on the right,"-   If there was a Two  on the left, we want to leave One  on the left and Two  on the right","-   If there was a One  on the left, we want to leave Zero on the left and Two  on the right","-   If there was a Done on the left, we want to leave Done on the left and Done on the right"]
Ngeneric:Invisible-Pin|pin@227||-52|65.5|||||ART_message(D4G1.5;)S[drained unless there was a Done on the left,"(equivalently: if pred[OneOrTwo] was HI before firing)"]
Ngeneric:Invisible-Pin|pin@228||-51.5|4.5|||||ART_message(D4G1.5;)S[Drained if there was a One on the left before firing.,"(equivalently: if pred[DoneOrTwo] was LO before firing)"]
Ngeneric:Invisible-Pin|pin@229||36.5|6|||||ART_message(D6G1.5;)S[filled if there wasn't a Done on the left before firing,(equivalently: if there wasn't a Done on the left AFTER firing)]
Ngeneric:Invisible-Pin|pin@230||37.5|64.5|||||ART_message(D6G1.5;)S[filled unconditionally,(we only leave Done's and Two's on the right)]
NWire_Pin|pin@234||-22|66||||
NWire_Pin|pin@235||-22|36.5||||
NWire_Pin|pin@236||-28|70.5||||
NWire_Pin|pin@237||-15|48.5||||
NWire_Pin|pin@238||-15|70.5||||
NWire_Pin|pin@239||-15|76||||
NWire_Pin|pin@240||-1.5|68||||
NWire_Pin|pin@242||29|34.5||||
NWire_Pin|pin@243||68.5|34.5||||
NWire_Pin|pin@244||74|38||||
NWire_Pin|pin@245||74|31||||
NWire_Pin|pin@246||74|34.5||||
Ngeneric:Invisible-Pin|pin@247||105|34|||||ART_message(D5G3;)S[load,"\"with",extreme,"prejudice\""]
IdriversM:predCond20wMC;1{ic}|predCond@0||-32|1|RR||D5G4;
IdriversM:predCond20wMC;1{ic}|predCond@1||-32|69|YRR||D5G4;
NPower|pwr@0||68.5|48||||
IdriversM:sucANDdri10;1{ic}|sucANDdr@0||19.5|3|Y||D5G4;
IdriversM:sucDri10;1{ic}|sucDri10@0||21|68|||D5G4;
Awire|fire|D5G2;||1800|predCond@0|in|-26|2|sucANDdr@0|inB|14.5|2
Awire|fire|D5G2;||2700|ctrAND4i@0|out|-1.5|64.5|pin@240||-1.5|68
Awire|net@319|||0|pin@120||-40.5|69|conn@2|y|-46|69
Awire|net@322|||0|pin@115||-42|1|conn@1|a|-46|1
Awire|net@324|||1800|pin@129||29|68|conn@3|a|32|68
Awire|net@345|||1800|pin@128||29|3|conn@0|a|31.5|3
Awire|net@346|||900|pin@242||29|34.5|pin@128||29|3
Awire|net@348|||900|pin@129||29|68|pin@130||29|36.5
Awire|net@369|||0|predCond@0|pred|-35|1|pin@115||-42|1
Awire|net@375|||0|sucDri10@0|in|17|68|pin@163||5|68
Awire|net@376|||1800|sucDri10@0|succ|25|68|pin@129||29|68
Awire|net@379|||0|pin@130||29|36.5|pin@165||18.5|36.5
Awire|net@383|||0|pin@127||29|34.5|pin@167||18|34.5
Awire|net@394|||2700|pin@178||-3.5|35.5|ctrAND4i@0|inC|-3.5|52.5
Awire|net@399|||900|ctrAND4i@0|inB|0.5|52.5|pin@181||0.5|34.5
Awire|net@400|||1800|pin@181||0.5|34.5|pin@167||18|34.5
Awire|net@401|||900|ctrAND4i@0|inA|2.5|52.5|pin@182||2.5|36.5
Awire|net@402|||1800|pin@182||2.5|36.5|pin@165||18.5|36.5
Awire|net@406|||2700|pin@115||-42|1|pin@180||-42|36.5
Awire|net@436|||2700|pin@206||-5.5|48.5|ctrAND4i@0|inD|-5.5|52.5
Awire|net@437|||900|pin@120||-40.5|69|pin@179||-40.5|34.5
Awire|net@442|||1800|sucANDdr@0|succ|24.5|3|pin@128||29|3
Awire|net@455|||0|pin@178||-3.5|35.5|pin@214||-5|35.5
Awire|net@459|||1800|pin@179||-40.5|34.5|nor2with@0|ina|-20.5|34.5
Awire|net@460|||1800|pin@180||-42|36.5|pin@235||-22|36.5
Awire|net@461|||1800|nor2with@0|out|-10|35.5|pin@214||-5|35.5
Awire|net@462|||900|nor2with@0|outaBar|-15|32.5|pin@218||-15|28.5
Awire|net@463|||0|pin@218||-15|28.5|pin@219||-23|28.5
Awire|net@466|||1800|predCond@0|cond|-26|4|pin@220||-23|4
Awire|net@475|||1800|pin@218||-15|28.5|pin@224||-7|28.5
Awire|net@477|||1800|pin@225||-7|4|sucANDdr@0|inA|14.5|4
Awire|net@482|||0|predCond@1|pred|-35|69|pin@120||-40.5|69
Awire|net@484|||1800|predCond@1|cond|-26|66|pin@234||-22|66
Awire|net@485|||1800|pin@235||-22|36.5|nor2with@0|inb|-16|36.5
Awire|net@486|||900|pin@234||-22|66|pin@235||-22|36.5
Awire|net@487|||0|pin@238||-15|70.5|pin@236||-28|70.5
Awire|net@488|||2700|pin@236||-28|70.5|predCond@1|mc|-28|71
Awire|net@489|||0|pin@206||-5.5|48.5|pin@237||-15|48.5
Awire|net@491|||2700|pin@237||-15|48.5|pin@238||-15|70.5
Awire|net@493|||1800|conn@6|y|-46|76|pin@239||-15|76
Awire|net@494|||900|pin@239||-15|76|pin@238||-15|70.5
Awire|net@496|||0|pin@163||5|68|predCond@1|in|-26|68
Awire|net@501|||900|pin@127||29|34.5|pin@242||29|34.5
Awire|net@503|||1800|pin@242||29|34.5|pin@243||68.5|34.5
Awire|net@507|||900|NMOS@1|d|68.5|29|NMOS@2|s|68.5|27.5
Awire|net@508|||2700|NMOS@1|s|68.5|33|pin@243||68.5|34.5
Awire|net@509|||900|PMOS@0|s|68.5|36|pin@243||68.5|34.5
Awire|net@510|||900|PMOS@1|s|68.5|41|PMOS@0|d|68.5|40
Awire|net@511|||2700|PMOS@1|d|68.5|45|pwr@0||68.5|48
Awire|net@512|||1800|PMOS@0|g|71.5|38|pin@244||74|38
Awire|net@513|||900|pin@246||74|34.5|pin@245||74|31
Awire|net@514|||0|pin@245||74|31|NMOS@1|g|71.5|31
Awire|net@515|||900|pin@244||74|38|pin@246||74|34.5
Awire|net@516|||0|conn@7|y|80|34.5|pin@246||74|34.5
Awire|net@517|||0|conn@8|y|80|43|PMOS@1|g|71.5|43
Awire|net@518|||0|conn@9|y|80|25.5|NMOS@2|g|71.5|25.5
Awire|predWasNotDoneAfterFiring|D5G1.5;RRR||900|pin@224||-7|28.5|pin@225||-7|4
Awire|predWasOneBeforeFiring|D5G1.5;RRRY0.5;||900|pin@219||-23|28.5|pin@220||-23|4
Eload||D5G2;X-3;|conn@9|a|U
EloadBar||D5G2;X-4.5;|conn@8|a|U
EloadVal|loadValBar|D5G2;X-6;|conn@7|a|U
Eload_or_master_clear||D5G2;X-11;|conn@6|a|U
Epred[TwoOrEmpty]|pred[DoneOrTwo]|D5G2;X-10.5;|conn@2|a|B
Epred[OneOrTwo]||D5G2;X13;|conn@1|a|B
Esucc[TwoOrEmpty]|succ[DoneOrTwo]|D5G2;X13.5;|conn@3|a|B
Esucc[OneOrTwo]||D5G2;X12.5;|conn@0|a|B
X