ship: Alu2

== Ports ===========================================================
data  in:   in1
data  in:   in2
data  in:   inOp
  constant ADD: 0
  constant SUB: 1
  constant MAX: 2
  constant MIN: 3

data  out:  out


== TeX ==============================================================

{\tt Alu2} is a ``two-input'' arithmetic logic unit.  It includes
logic for performing arithmetic operations on a pair of arguments.
Currently this includes
addition ({\sc add}),
subtraction ({\sc sub}),
maximum ({\sc max}), and
minimum ({\sc min}).

\subsection*{Semantics}

When a value is present at each of {\tt in1}, {\tt in2} and {\tt
inOp}, these three values are consumed.  Based on the value consumed
at {\tt inOp}, the requested operation is performed on the values
consumed from {\tt in1} and {\tt in2}.  The result of this operation
is then made available at {\tt out}.

\subsection*{To Do}

The {\it link bit} and other features of \cite{ies31} are not yet
implemented.

The carry-in, carry-out, zero-test, negative-test, and overflow-test
flags typically present in a conventional processor ALU are also not
yet implemented.

== Fleeterpreter ====================================================
public void service() {
  if (box_in1.dataReadyForShip() &&
      box_in2.dataReadyForShip() &&
      box_inOp.dataReadyForShip() &&
      box_out.readyForDataFromShip()) {
      long a      = box_in1.removeDataForShip();
      long b      = box_in2.removeDataForShip();
      long op     = box_inOp.removeDataForShip();
      switch((int)op) {
          case 0: box_out.addDataFromShip(a+b); // ADD
              break;
          case 1: box_out.addDataFromShip(a-b); // SUB
              break;
          case 2: box_out.addDataFromShip(Math.max(a,b)); // MAX
              break;
          case 3: box_out.addDataFromShip(Math.min(a,b)); // MIN
              break;
          default: box_out.addDataFromShip(0);
              break;
      }
  }
}

== FleetSim ==============================================================

== FPGA ==============================================================

  always @(posedge clk) begin
    if (!rst) begin
      `reset
    end else begin
      if (out_r    && out_a)    out_r    <= 0;
      if (!in1_r   && in1_a)    in1_a    <= 0;
      if (!in2_r   && in2_a)    in2_a    <= 0;
      if (!inOp_r  && inOp_a)   inOp_a   <= 0;
      if (!out_r && !out_a && in1_r && !in1_a && in2_r && !in2_a && inOp_r && !inOp_a) begin
        out_r <= 1;
        in1_a <= 1;
        in2_a <= 1;
        inOp_a <= 1;
        case (inOp_d)
          0: out_d <= in1_d + in2_d;
          1: out_d <= in1_d - in2_d;
          2: out_d <= in1_d > in2_d ? in1_d : in2_d;
          3: out_d <= in1_d > in2_d ? in2_d : in1_d;
          default: out_d <= 0;
        endcase        
      end
    end
  end

== Test ==============================================================================
// expected output
#ship debug : Debug
#ship alu   : Alu2

#expect 17
#expect 1
#expect 8
#expect 9

debug.in:   [*] take, deliver;
alu.in1:
  literal 9; load repeat counter with 4; deliver;

alu.in2:
  literal 8; load repeat counter with 4; deliver;

alu.inOp:
 literal Alu2.inOp[ADD]; deliver;
 literal Alu2.inOp[SUB]; deliver;
 literal Alu2.inOp[MIN]; deliver;
 literal Alu2.inOp[MAX]; deliver;

alu.in1:    [*] take, deliver;
alu.in2:    [*] take, deliver;
alu.out:    [*] take, sendto debug.in;



== Contributors =========================================================
Adam Megacz <megacz@cs.berkeley.edu>