ship: Alu2

== Ports ===========================================================
data  in:   in1
data  in:   in2
data  in:   inOp

data  out:  out

== Constants ========================================================
ADD: add the two arguments; treat link as carry
SUB: subtract the two arguments; treat link as carry

== TeX ==============================================================
This ship is a two-input arithmetic unit.  It features several
opcodes, such as {\tt ADD} and {\tt SUB}.  In my opinion, it is
niftycool.

== Fleeterpreter ====================================================
public void service() {
  if (box_in1.dataReadyForShip() &&
      box_in2.dataReadyForShip() &&
      box_inOp.dataReadyForShip() &&
      box_out.readyForItemFromShip()) {
      int a      = box_in1.removeDataForShip();
      int b      = box_in2.removeDataForShip();
      int op     = box_inOp.removeDataForShip();
      switch(op) {
          case 0: box_out.addDataFromShip(a+b); // ADD
              break;
          case 1: box_out.addDataFromShip(a-b); // SUB
              break;
          case 2: box_out.addDataFromShip(a*b); // MUL
              break;
          case 3: box_out.addDataFromShip(a/b); // DIV
              break;
          case 4: box_out.addDataFromShip(a%b); // REM
              break;
          default: box_out.addDataFromShip(0);
              break;
      }
  }
}

== ArchSim ==============================================================

== FPGA ==============================================================
`include "macros.v"

module alu2 (clk, 
             a_r,    a_a_,  a_d,
             b_r,    b_a_,  b_d,
             op_r,   op_a_, op_d,
             out_r_, out_a, out_d_);

  input  clk;
  `input(a_r,    a_a,    a_a_,  [(`DATAWIDTH-1):0], a_d)
  `input(b_r,    b_a,    b_a_,  [(`DATAWIDTH-1):0], b_d)
  `input(op_r,   op_a,   op_a_, [(`DATAWIDTH-1):0], op_d)
  `output(out_r, out_r_, out_a, [(`DATAWIDTH-1):0], out_d_)
  `defreg(out_d_, [(`DATAWIDTH-1):0], out_d)

  reg                    have_a;
  reg [(`DATAWIDTH-1):0] reg_a;
  reg                    have_b;
  reg [(`DATAWIDTH-1):0] reg_b;
  reg                    have_op;
  reg [(`DATAWIDTH-1):0] reg_op;

  always @(posedge clk) begin
    if (!have_a) begin
      `onread(a_r, a_a) have_a = 1; reg_a = a_d; end
      end
    if (!have_b) begin
      `onread(b_r, b_a) have_b = 1; reg_b = b_d; end
      end
    if (!have_op) begin
      `onread(op_r, op_a) have_op = 1; reg_op = op_d; end
      end
  
    if (have_a && have_b && have_op) begin
      case (reg_op)
        0: out_d = reg_a + reg_b;
        1: out_d = reg_a - reg_b;
        //2: out_d = reg_a * reg_b; // will not synthesize --AM
        //3: out_d = reg_a / reg_b; // will not synthesize --AM
        //4: out_d = reg_a % reg_b; // will not synthesize --AM
        default: out_d = 0;
      endcase        
      `onwrite(out_r, out_a)
        have_a  = 0;
        have_b  = 0;
        have_op = 0;
      end
    end
  end

endmodule



== Contributors =========================================================
Adam Megacz <megacz@cs.berkeley.edu>