ship: Alu2b

== Ports ===========================================================
data  in:   in1.add
data  in:   in1.sub
data  in:   in1.max
data  in:   in1.min

data  in:   in2

data  out:  out

== Constants ========================================================

== TeX ==============================================================
This ship is a two-input arithmetic unit.  The first input is split
into multiple virtual destinations that control the operation to be
performed.

== Fleeterpreter ====================================================
public void service() {
  if (!box_out.readyForDataFromShip() ||
      !box_in1.dataReadyForShip() ||
      !box_in2.dataReadyForShip()) return;

  Packet selector = box_in1.removePacketForShip();
  String port = selector.destination.getDestinationName();
  long a      = selector.value;
  long b      = box_in2.removeDataForShip();

  if (port.equals("add")) {
    box_out.addDataFromShip(a+b); // ADD
  } else if (port.equals("sub")) {
    box_out.addDataFromShip(a-b); // SUB
  } else if (port.equals("max")) {
    box_out.addDataFromShip(Math.max(a,b)); // MAX
  } else if (port.equals("min")) {
    box_out.addDataFromShip(Math.min(a,b)); // MIN
  } else {
    box_out.addDataFromShip(0);
  }
}

== FleetSim ==============================================================

== FPGA ==============================================================

  reg                    have_a;
  reg [(`PACKET_WIDTH-1):0] reg_a;
  reg                    have_b;
  reg [(`DATAWIDTH-1):0] reg_b;

  reg a_val;

  always @(posedge clk) begin
    if (!have_a) begin
      `onread(in1_r, in1_a) have_a = 1; reg_a = in1_d; end
      end
    if (!have_b) begin
      `onread(in2_r, in2_a) have_b = 1; reg_b = in2_d; end
      end
  
    if (have_a && have_b) begin
      a_val = reg_a[`DATAWIDTH-1:0];
      case (reg_a[`PACKET_WIDTH-1:`DATAWIDTH])
        0: out_d = a_val + reg_b;
        1: out_d = a_val - reg_b;
        2: out_d = a_val > reg_b ? a_val : reg_b;
        3: out_d = a_val > reg_b ? reg_b : a_val;
        default: out_d = 0;
      endcase        
      `onwrite(out_r, out_a)
        have_a  = 0;
        have_b  = 0;
      end
    end
  end




== Contributors =========================================================
Adam Megacz <megacz@cs.berkeley.edu>
Amir Kamil  <kamil@cs.berkeley.edu>