ship: Video == Ports =========================================================== data in: inX data in: inY data in: inData percolate up: dvi_d0 1 percolate up: dvi_d1 1 percolate up: dvi_d2 1 percolate up: dvi_d3 1 percolate up: dvi_d4 1 percolate up: dvi_d5 1 percolate up: dvi_d6 1 percolate up: dvi_d7 1 percolate up: dvi_d8 1 percolate up: dvi_d9 1 percolate up: dvi_d10 1 percolate up: dvi_d11 1 percolate up: dvi_h 1 percolate up: dvi_v 1 percolate up: dvi_xclk_n 1 percolate up: dvi_xclk_p 1 percolate up: dvi_de 1 percolate up: dvi_reset_b 1 percolate down: gpio_sw_c 1 percolate up: gpio_led_c 1 percolate up: gpio_led_e 1 percolate up: gpio_led_n 1 percolate up: gpio_led_s 1 percolate up: gpio_led_w 1 percolate up: gpio_led_0 1 percolate up: gpio_led_1 1 percolate up: gpio_led_2 1 percolate up: gpio_led_3 1 percolate up: gpio_led_4 1 percolate up: gpio_led_5 1 percolate up: gpio_led_6 1 percolate up: gpio_led_7 1 percolate up: dvi_iic_scl 1 percolate inout: dvi_iic_sda 1 == FPGA ============================================================== wire [9:0] x_coord; wire [9:0] y_coord; wire data_valid_ext; wire clk_fb; wire pix_clk; wire[7:0] dvi_green; wire[7:0] dvi_red; wire[7:0] dvi_blue; assign dvi_reset_b = 1; assign dvi_de = data_valid_ext; vga_timing_generator #( .WIDTH(640), .H_FP(16), .H_SYNC(96), .H_BP(48), .HEIGHT(480), .V_FP(12), .V_SYNC(2), .V_BP(31), .HEIGHT_BITS(10), .WIDTH_BITS(10), .DATA_DELAY(0) ) my_vga_timing_generator ( .rst(rst), .clk(pix_clk), .hsync(dvi_h), .vsync(dvi_v), .X_COORD(x_coord), .Y_COORD(y_coord), .DATA_VALID(), .DATA_VALID_EXT(data_valid_ext), .PIXEL_COUNT() ); ODDR #( .DDR_CLK_EDGE("OPPOSITE_EDGE"), // "OPPOSITE_EDGE" or "SAME_EDGE" .INIT(1'b0), // Initial value for Q port ('1' or '0') .SRTYPE("SYNC") // Reset Type ("ASYNC" or "SYNC") ) ODDR_xclk_p ( .Q(dvi_xclk_p), // 1-bit DDR output .C(pix_clk), // 1-bit clock input .CE(1), // 1-bit clock enable input .D1(1), // 1-bit data input (positive edge) .D2(0), // 1-bit data input (negative edge) .R(0), // 1-bit reset input .S(0) // 1-bit set input ); ODDR #( .DDR_CLK_EDGE("OPPOSITE_EDGE"), // "OPPOSITE_EDGE" or "SAME_EDGE" .INIT(1'b0), // Initial value for Q port ('1' or '0') .SRTYPE("SYNC") // Reset Type ("ASYNC" or "SYNC") ) ODDR_xclk_n ( .Q(dvi_xclk_n), // 1-bit DDR output .C(pix_clk), // 1-bit clock input .CE(1), // 1-bit clock enable input .D1(0), // 1-bit data input (positive edge) .D2(1), // 1-bit data input (negative edge) .R(0), // 1-bit reset input .S(0) // 1-bit set input ); i2c_video_programmer my_i2c_video_programmer_i ( .CLK200Mhz(clk), .RST(rst), .I2C_SDA(dvi_iic_sda), .I2C_SCL(dvi_iic_scl)); DCM_BASE #( .CLKDV_DIVIDE(4.0), // Divide by: 1.5,2.0,2.5,3.0,3.5,4.0,4.5,5.0,5.5,6.0,6.5 .CLKFX_DIVIDE(16), // Can be any interger from 1 to 32 .CLKFX_MULTIPLY(2), // Can be any integer from 2 to 32 .CLKIN_DIVIDE_BY_2("FALSE"), // TRUE/FALSE to enable CLKIN divide by two feature .CLKIN_PERIOD(10.0), // Specify period of input clock in ns from 1.25 to 1000.00 .CLKOUT_PHASE_SHIFT("NONE"), // Specify phase shift mode of NONE or FIXED .CLK_FEEDBACK("1X"), // Specify clock feedback of NONE or 1X .DCM_AUTOCALIBRATION("TRUE"), // DCM calibrartion circuitry TRUE/FALSE .DCM_PERFORMANCE_MODE("MAX_SPEED"), // Can be MAX_SPEED or MAX_RANGE .DESKEW_ADJUST("SYSTEM_SYNCHRONOUS"), // SOURCE_SYNCHRONOUS, SYSTEM_SYNCHRONOUS or .DFS_FREQUENCY_MODE("HIGH"), // LOW or HIGH frequency mode for frequency synthesis .DLL_FREQUENCY_MODE("LOW"), // LOW, HIGH, or HIGH_SER frequency mode for DLL .DUTY_CYCLE_CORRECTION("TRUE"), // Duty cycle correction, TRUE or FALSE .FACTORY_JF(16'hF0F0), // FACTORY JF Values Suggested to be set to X"F0F0" .PHASE_SHIFT(0), // Amount of fixed phase shift from -255 to 1023 .STARTUP_WAIT("FALSE") // Delay configuration DONE until DCM LOCK, TRUE/FALSE ) DCM_BASE_dvi ( .CLK0(clk_fb), .CLKDV(pix_clk), .CLKFB(clk_fb), .CLKIN(clk), .RST(rst) ); ODDR ODDR_dvi_d0 (dvi_d0, pix_clk, 1, dvi_green[4], dvi_blue[0], ~data_valid_ext, 0); ODDR ODDR_dvi_d1 (dvi_d1, pix_clk, 1, dvi_green[5], dvi_blue[1], ~data_valid_ext, 0); ODDR ODDR_dvi_d2 (dvi_d2, pix_clk, 1, dvi_green[6], dvi_blue[2], ~data_valid_ext, 0); ODDR ODDR_dvi_d3 (dvi_d3, pix_clk, 1, dvi_green[7], dvi_blue[3], ~data_valid_ext, 0); ODDR ODDR_dvi_d4 (dvi_d4, pix_clk, 1, dvi_red[0], dvi_blue[4], ~data_valid_ext, 0); ODDR ODDR_dvi_d5 (dvi_d5, pix_clk, 1, dvi_red[1], dvi_blue[5], ~data_valid_ext, 0); ODDR ODDR_dvi_d6 (dvi_d6, pix_clk, 1, dvi_red[2], dvi_blue[6], ~data_valid_ext, 0); ODDR ODDR_dvi_d7 (dvi_d7, pix_clk, 1, dvi_red[3], dvi_blue[7], ~data_valid_ext, 0); ODDR ODDR_dvi_d8 (dvi_d8, pix_clk, 1, dvi_red[4], dvi_green[0], ~data_valid_ext, 0); ODDR ODDR_dvi_d9 (dvi_d9, pix_clk, 1, dvi_red[5], dvi_green[1], ~data_valid_ext, 0); ODDR ODDR_dvi_d10 (dvi_d10, pix_clk, 1, dvi_red[6], dvi_green[2], ~data_valid_ext, 0); ODDR ODDR_dvi_d11 (dvi_d11, pix_clk, 1, dvi_red[7], dvi_green[3], ~data_valid_ext, 0); reg we; wire [2:0] mem_out; wire [18:0] inAddr; wire [18:0] vga_pixel_addr_; reg [18:0] vga_pixel_addr; assign inAddr = inX_d + { inY_d[8:0], 7'b0000000 } + { inY_d[8:0], 10'b0000000000 }; assign vga_pixel_addr_ = x_coord + { y_coord[8:0], 7'b0000000 } + { y_coord[8:0], 10'b0000000000 }; assign dvi_red = { mem_out[2], 7'b0 }; assign dvi_green = { mem_out[1], 7'b0 }; assign dvi_blue = { mem_out[0], 7'b0 }; vram vram(clk, ~rst, we, inAddr[18:0], vga_pixel_addr, inData_d, , mem_out); always @(posedge pix_clk) begin vga_pixel_addr <= vga_pixel_addr_; end always @(posedge clk) begin if (rst) begin `reset end else begin `cleanup if (`inX_full && `inY_full && `inData_full) begin we <= 1; `drain_inX `drain_inY `drain_inData end else begin we <= 0; end end end == UCF =============================================================== #Net "dvi_0/dvi_xclk_p_unbuffered" PERIOD = 5 ns HIGH 50%; NET dvi_d0 LOC="AB8" | IOSTANDARD="LVDCI_33"; # Bank 22, Vcco=3.3V, DCI using 49.9 ohm resistors NET dvi_d1 LOC="AC8" | IOSTANDARD="LVDCI_33"; # Bank 22, Vcco=3.3V, DCI using 49.9 ohm resistors NET dvi_d2 LOC="AN12" | IOSTANDARD="LVDCI_33"; # Bank 22, Vcco=3.3V, DCI using 49.9 ohm resistors NET dvi_d3 LOC="AP12" | IOSTANDARD="LVDCI_33"; # Bank 22, Vcco=3.3V, DCI using 49.9 ohm resistors NET dvi_d4 LOC="AA9" | IOSTANDARD="LVDCI_33"; # Bank 22, Vcco=3.3V, DCI using 49.9 ohm resistors NET dvi_d5 LOC="AA8" | IOSTANDARD="LVDCI_33"; # Bank 22, Vcco=3.3V, DCI using 49.9 ohm resistors NET dvi_d6 LOC="AM13" | IOSTANDARD="LVDCI_33"; # Bank 22, Vcco=3.3V, DCI using 49.9 ohm resistors NET dvi_d7 LOC="AN13" | IOSTANDARD="LVDCI_33"; # Bank 22, Vcco=3.3V, DCI using 49.9 ohm resistors NET dvi_d8 LOC="AA10" | IOSTANDARD="LVDCI_33"; # Bank 22, Vcco=3.3V, DCI using 49.9 ohm resistors NET dvi_d9 LOC="AB10" | IOSTANDARD="LVDCI_33"; # Bank 22, Vcco=3.3V, DCI using 49.9 ohm resistors NET dvi_d10 LOC="AP14" | IOSTANDARD="LVDCI_33"; # Bank 22, Vcco=3.3V, DCI using 49.9 ohm resistors NET dvi_d11 LOC="AN14" | IOSTANDARD="LVDCI_33"; # Bank 22, Vcco=3.3V, DCI using 49.9 ohm resistors NET dvi_de LOC="AE8" | IOSTANDARD="LVDCI_33" | SLEW=FAST; # Bank 22, Vcco=3.3V, DCI using 49.9 ohm resistors NET dvi_reset_b LOC="AK6" | IOSTANDARD="LVCMOS33"; # Bank 18, Vcco=3.3V, No DCI NET dvi_h LOC="AM12" | IOSTANDARD="LVDCI_33" | SLEW=FAST; # Bank 22, Vcco=3.3V, DCI using 49.9 ohm resistors NET dvi_v LOC="AM11" | IOSTANDARD="LVDCI_33" | SLEW=FAST; # Bank 22, Vcco=3.3V, DCI using 49.9 ohm resistors NET dvi_xclk_n LOC="AL10" | IOSTANDARD="LVCMOS33" | DRIVE=24 | SLEW=FAST; # Bank 22, Vcco=3.3V, DCI using 49.9 ohm resistors NET dvi_xclk_p LOC="AL11" | IOSTANDARD="LVCMOS33" | DRIVE=24 | SLEW=FAST; # Bank 22, Vcco=3.3V, DCI using 49.9 ohm resistors NET dvi_gpio1 LOC="N30" | IOSTANDARD="LVCMOS18"; # Bank 15, Vcco=1.8V, DCI using 49.9 ohm resistors NET dvi_iic_scl LOC="U27" | PULLUP | IOSTANDARD="LVCMOS18"; # Bank 15, Vcco=1.8V, DCI using 49.9 ohm resistors NET dvi_iic_sda LOC="T29" | PULLUP | IOSTANDARD="LVCMOS18"; # Bank 15, Vcco=1.8V, DCI using 49.9 ohm resistors NET gpio_sw_c LOC="AJ6" | IOSTANDARD="LVCMOS33"; # Bank 18, Vcco=3.3V, No DCI NET gpio_led_c LOC="E8"; # Bank 20, Vcco=3.3V, DCI using 49.9 ohm resistors NET gpio_led_e LOC="AG23"; # Bank 2, Vcco=3.3V NET gpio_led_n LOC="AF13"; # Bank 2, Vcco=3.3V NET gpio_led_s LOC="AG12"; # Bank 2, Vcco=3.3V NET gpio_led_w LOC="AF23"; # Bank 2, Vcco=3.3V NET gpio_led_0 LOC="H18"; # Bank 3, Vcco=2.5V, No DCI NET gpio_led_1 LOC="L18"; # Bank 3, Vcco=2.5V, No DCI NET gpio_led_2 LOC="G15"; # Bank 3, Vcco=2.5V, No DCI NET gpio_led_3 LOC="AD26" | IOSTANDARD="LVCMOS18"; # Bank 21, Vcco=1.8V, DCI using 49.9 ohm resistors NET gpio_led_4 LOC="G16"; # Bank 3, Vcco=2.5V, No DCI NET gpio_led_5 LOC="AD25" | IOSTANDARD="LVCMOS18"; # Bank 21, Vcco=1.8V, DCI using 49.9 ohm resistors NET gpio_led_6 LOC="AD24" | IOSTANDARD="LVCMOS18"; # Bank 21, Vcco=1.8V, DCI using 49.9 ohm resistors NET gpio_led_7 LOC="AE24" | IOSTANDARD="LVCMOS18"; # Bank 21, Vcco=1.8V, DCI using 49.9 ohm resistors == TeX ============================================================== == Fleeterpreter ==================================================== public void service() { } == FleetSim ============================================================== == Constants ========================================================= == Test ============================================================== #expect 0 #expect 0 #expect 0 #ship debug : Debug #ship video : Dvi video.inX: set word=0; deliver; send token to debug.in; video.inY: set word=0; deliver; send token to debug.in; video.inData: set word=0; deliver; send token to debug.in; debug.in: set word=0; set ilc=*; recv token, deliver; == Contributors ========================================================= Adam Megacz