ship: Execute

== Ports ===========================================================
data  in:   in

== Constants ========================================================
== TeX ==============================================================
== Fleeterpreter ====================================================
    public void service() {
        //throw new Error("the Execute ship is only for FPGA simulations");
    }

== FleetSim ==============================================================
== FPGA ==============================================================
`include "macros.v"

module execute (clk, in_r,     in_a_,   in_d,
                     ihorn_r_, ihorn_a, ihorn_d_,
                     dhorn_r_, dhorn_a, dhorn_d_
               );
  input clk;

  `input(in_r,     in_a,     in_a_,   [(`DATAWIDTH-1):0],         in_d)
  `output(ihorn_r, ihorn_r_, ihorn_a, [(`INSTRUCTION_WIDTH-1):0], ihorn_d_)
  `defreg(ihorn_d_,                   [(`INSTRUCTION_WIDTH-1):0], ihorn_d)
  `output(dhorn_r, dhorn_r_, dhorn_a, [(`PACKET_WIDTH-1):0],      dhorn_d_)
  `defreg(dhorn_d_,                   [(`PACKET_WIDTH-1):0],      dhorn_d)

  reg ihorn_full;
  reg dhorn_full;

  always @(posedge clk) begin
    if (ihorn_full) begin
      `onwrite(ihorn_r, ihorn_a)
        ihorn_full = 0;
      end
    end else if (dhorn_full) begin
      `onwrite(dhorn_r, dhorn_a)
        dhorn_full = 0;
      end
    end else begin
      `onread(in_r, in_a)
        case (in_d[(`INSTRUCTION_WIDTH-1):(`INSTRUCTION_WIDTH-2)])
          0: begin
              ihorn_full  = 1;
              ihorn_d = in_d;
              end
          //01:
          2: begin
              dhorn_full  = 1;
              `packet_data(dhorn_d) = in_d[23:0];
              `packet_dest(dhorn_d) = in_d[34:24];
              end
          //11:
        endcase
      end
    end
  end


endmodule


== Test ==============================================================================
#skip
#ship debug : Debug
#expect 0
0: sendto debug.in;

== Contributors =========================================================
Adam Megacz <megacz@cs.berkeley.edu>