ship: Fifo

== Ports ===========================================================
data  in:   in
data  out:  out

== Constants ========================================================
== TeX ==============================================================
== Fleeterpreter ====================================================
    private Queue<Long> fifo = new LinkedList<Long>();
    public void service() {
        if (box_in.dataReadyForShip()) {
            fifo.add(box_in.removeDataForShip());
        }
        if (box_out.readyForDataFromShip() && fifo.size() > 0) {
            box_out.addDataFromShip(fifo.remove());
        }
    }

== FleetSim ==============================================================
== FPGA ==============================================================
`include "macros.v"

// fifo *ship*: a 16-deep word-wide fifo
module fifo (clk, 
             in_r,  in_a, in_d,
             out_r, out_a, out_d);

  input  clk;
  input  in_r;
  input  out_a;
  output in_a;
  output out_r;
  input  [(`DATAWIDTH-1):0] in_d;
  output [(`DATAWIDTH-1):0] out_d;

  wire   [(`DATAWIDTH-1):0] d12;
  wire   [(`DATAWIDTH-1):0] d23;
  wire   [(`DATAWIDTH-1):0] d34;

  fifo4 s1(clk, in_r, in_a, in_d, r12, a12,     d12);
  fifo4 s2(clk, r12,  a12,  d12,  r23, a23,     d23);
  fifo4 s3(clk, r23,  a23,  d23,  r34, a34,     d34);
  fifo4 s4(clk, r34,  a34,  d34,  out_r, out_a, out_d);

endmodule

== Test =================================================================
// expected output
#expect 9

// ships required in order to run this code
#ship debug        : Debug
#ship fifo         : Fifo

debug.in:   [*] take, deliver;
9:            sendto fifo.in;
fifo.in:
  take;
  [100] deliver;
fifo.out:
  (99) take, sendto fifo.in;
  (1)  take, sendto debug.in;



== Contributors =========================================================
Adam Megacz <megacz@cs.berkeley.edu>