ship: Memory

== Ports ===========================================================
data  in:    inCBD
data  in:    inAddr.read
data  in:    inAddr.write
data  in:    inAddr.readMany
data  in:    inAddr.writeMany
data  in:    inData
data  in:    inStride
data  in:    inCount

data  out:   out

== Fleeterpreter ====================================================
    private long[] mem = new long[0];
    public long readMem(int addr) { return mem[addr]; }
    public void writeMem(int addr, long val) {
        if (addr >= mem.length) {
            long[] newmem = new long[addr * 2 + 1];
            System.arraycopy(mem, 0, newmem, 0, mem.length);
            mem = newmem;
        }
        mem[addr] = val;
    }

    public void dispatch(int addr, int size) {
        for(int i=addr; i<addr+size; i++) {
            Instruction instr = ((Interpreter)getFleet()).readInstruction(readMem(i));
            ((Interpreter)getFleet()).dispatch(instr, i);
        }
    }

    public void boot(byte[] instructions) {
        Interpreter fleet = (Interpreter)getFleet();
        // load the iscratch and take note of the 0-address INCBD
        long launch = 0;
        for(int i=0; i<instructions.length; i+=6) {
            long word = 0;
            for(int j=0; j<6; j++)
                word = (word << 8) | (instructions[i+j] & 0xff);
            writeMem(i/6, word);
            if (i==0) launch = word;
        }

        // dispatch the 0-address INCBD
        int base = (int)(launch >> 6);
        base = base & ~(0xffffffff << 18);
        int size = (int)launch;
        size = size & ~(0xffffffff <<  6);
        dispatch(base, size);
    }

    private long stride = 0;
    private long count = 0;
    private long addr = 0;
    private boolean writing = false;

    public void service() {
        if (box_inCBD.dataReadyForShip()) {
            long val = box_inCBD.removeDataForShip();
            long addr = val >> 6;
            long size = val & 0x3f;
            dispatch((int)addr, (int)size);
        }
        if (count > 0 && writing) {
            if (box_inData.dataReadyForShip() && box_out.readyForDataFromShip()) {
               writeMem((int)addr, box_inData.removeDataForShip());
               box_out.addDataFromShip(0);
               count--;
               addr += stride;
            }

        } else if (count > 0 && !writing) {
            if (box_out.readyForDataFromShip()) {
               box_out.addDataFromShip(readMem((int)addr));
               count--;
               addr += stride;
            }

        } else if (box_inAddr.dataReadyForShip() && box_out.readyForDataFromShip()) {
            Packet packet = box_inAddr.peekPacketForShip();
            if (packet.destination.getDestinationName().equals("read")) {
                box_out.addDataFromShip(readMem((int)box_inAddr.removeDataForShip()));
            } else if (packet.destination.getDestinationName().equals("write") && box_inData.dataReadyForShip()) {
                writeMem((int)box_inAddr.removeDataForShip(),
                         box_inData.removeDataForShip());
                box_out.addDataFromShip(0);
            } else if (packet.destination.getDestinationName().equals("writeMany")
                       && box_inStride.dataReadyForShip()
                       && box_inCount.dataReadyForShip()) {
                addr = box_inAddr.removeDataForShip();
                stride = box_inStride.removeDataForShip();
                count = box_inCount.removeDataForShip();
                writing = true;
            } else if (packet.destination.getDestinationName().equals("readMany")
                       && box_inStride.dataReadyForShip()
                       && box_inCount.dataReadyForShip()) {
                addr = box_inAddr.removeDataForShip();
                stride = box_inStride.removeDataForShip();
                count = box_inCount.removeDataForShip();
                writing = false;
            }
        }
    }

== FleetSim ==============================================================

== FPGA ==============================================================
`include "macros.v"
`define BRAM_ADDR_WIDTH 14
`define BRAM_DATA_WIDTH `INSTRUCTION_WIDTH
`define BRAM_NAME some_bram
`include "bram.inc"

module memory (clk, 
               cbd_r,          cbd_a_,         cbd_d,
               in_addr_r,      in_addr_a_,     in_addr_d,
               write_data_r,   write_data_a_,  write_data_d,
               stride_r,       stride_a_,      stride_d,
               count_r,        count_a_,       count_d,
               out_r_,         out_a,          out_d_,
               preload_r,      preload_a_,     preload_d,
               ihorn_r_,       ihorn_a,        ihorn_d_,
               dhorn_r_,       dhorn_a,        dhorn_d_
              );

  input  clk;
  `input(in_addr_r,      in_addr_a,     in_addr_a_,     [(2+`DATAWIDTH-1):0],       in_addr_d)
  `input(write_data_r,   write_data_a,  write_data_a_,  [(`DATAWIDTH-1):0],         write_data_d)
  `input(stride_r,       stride_a,      stride_a_,      [(`DATAWIDTH-1):0],         stride_d)
  `input(count_r,        count_a,       count_a_,       [(`DATAWIDTH-1):0],         count_d)
  `output(out_r,         out_r_,        out_a,          [(`DATAWIDTH-1):0],         out_d_)
  //`defreg(out_d_,                                     [(`DATAWIDTH-1):0],         out_d)

  `input(preload_r,      preload_a,     preload_a_,     [(`DATAWIDTH-1):0],         preload_d)
  `input(cbd_r,          cbd_a,         cbd_a_,         [(`DATAWIDTH-1):0],         cbd_d)
  `output(ihorn_r,       ihorn_r_,      ihorn_a,        [(`INSTRUCTION_WIDTH-1):0], ihorn_d_)
  `defreg(ihorn_d_,                                     [(`INSTRUCTION_WIDTH-1):0], ihorn_d)
  `output(dhorn_r,       dhorn_r_,      dhorn_a,        [(`PACKET_WIDTH-1):0],      dhorn_d_)
  `defreg(dhorn_d_,                                     [(`PACKET_WIDTH-1):0],      dhorn_d)

  reg ihorn_full;
  initial ihorn_full = 0;
  reg dhorn_full;
  initial dhorn_full = 0;
  reg command_valid;
  initial command_valid = 0;

  reg [(`BRAM_ADDR_WIDTH-1):0]    preload_pos;
  reg [(`BRAM_ADDR_WIDTH-1):0]    preload_size;
  initial preload_size = 0;

  reg [(`BRAM_ADDR_WIDTH-1):0]    current_instruction_read_from;
  reg [(`BRAM_ADDR_WIDTH-1):0]    temp_base;
  reg [(`CODEBAG_SIZE_BITS-1):0]  temp_size;
  reg [(`BRAM_ADDR_WIDTH-1):0]    cbd_base;
  reg [(`CODEBAG_SIZE_BITS-1):0]  cbd_size;
  reg [(`CODEBAG_SIZE_BITS-1):0]  cbd_pos;
  reg [(`INSTRUCTION_WIDTH-1):0]  command;
  reg [(`BRAM_DATA_WIDTH-1):0]    ram [((1<<(`BRAM_ADDR_WIDTH))-1):0];
  reg                             send_done;
  reg                             send_read;

  reg [(`INSTRUCTION_WIDTH-(2+`DESTINATION_ADDRESS_BITS)):0] temp;
  reg [(`DATAWIDTH-1):0]                                     data;

  reg                             write_flag;
  reg [(`BRAM_ADDR_WIDTH-1):0]    in_addr;
  reg [(`BRAM_DATA_WIDTH-1):0]    write_data;

  wire [(`BRAM_DATA_WIDTH-1):0]   ramread;

  reg command_valid_read;
  initial command_valid_read = 0;

  reg launched;
  initial launched = 0;

  some_bram mybram(clk, write_flag, in_addr, current_instruction_read_from, write_data, not_connected, ramread);
  assign out_d_ = ramread;

  always @(posedge clk) begin

    write_flag <= 0;

    if (!in_addr_r && in_addr_a) in_addr_a = 0;
    if (!write_data_r && write_data_a) write_data_a = 0;

    if (command_valid_read) begin
      command_valid_read  <= 0;
      command_valid       <= 1;

    end else  if (send_done) begin
      `onwrite(out_r, out_a)
        send_done <= 0;
      end

    end else  if (send_read) begin
      `onwrite(out_r, out_a)
        send_read <= 0;
      end

    end else if (in_addr_r && !in_addr_d[`DATAWIDTH]) begin
      in_addr_a                        = 1;
      send_read                       <= 1;
      current_instruction_read_from   <= in_addr_d[(`DATAWIDTH-1):0];

    end else if (in_addr_r && in_addr_d[`DATAWIDTH] && write_data_r) begin
      in_addr_a          = 1;
      write_data_a       = 1;
      send_done         <= 1;
      write_flag        <= 1;
      in_addr           <= in_addr_d[(`DATAWIDTH-1):0];
      write_data        <= write_data_d;

    end else if (ihorn_full && launched) begin
      `onwrite(ihorn_r, ihorn_a)
        ihorn_full <= 0;
      end

    end else if (dhorn_full) begin
      `onwrite(dhorn_r, dhorn_a)
        dhorn_full <= 0;
      end

    end else if (command_valid) begin
      command_valid <= 0;
      command = ramread;
      case (command[(`INSTRUCTION_WIDTH-1):(`INSTRUCTION_WIDTH-2)])
        0: begin
            ihorn_full  <= 1;
            ihorn_d     <= command;
           end
        1: begin
            dhorn_full  <= 1;
            temp    = command[(`INSTRUCTION_WIDTH-(2+`DESTINATION_ADDRESS_BITS)):0];
            temp    = temp + ( { current_instruction_read_from, {(`CODEBAG_SIZE_BITS){1'b0}} });
            data[(`DATAWIDTH-1):(`CODEBAG_SIZE_BITS)] = temp;
            data[(`CODEBAG_SIZE_BITS-1):0]            = command[(`CODEBAG_SIZE_BITS-1):0];
            `packet_data(dhorn_d) <= temp;
            `packet_dest(dhorn_d) <=
                  command[(`INSTRUCTION_WIDTH-3):(`INSTRUCTION_WIDTH-(3+`DESTINATION_ADDRESS_BITS)+1)];
           end
        2: begin
            dhorn_full            <= 1;
            `packet_data(dhorn_d) <= { {(`DATAWIDTH-24){command[23]}}, command[23:0] };
            `packet_dest(dhorn_d) <= command[34:24];
           end
        3: begin
            dhorn_full            <= 1;
            `packet_data(dhorn_d) <= { {(`DATAWIDTH-24){command[23]}}, command[23:0] } + current_instruction_read_from;
            `packet_dest(dhorn_d) <= command[34:24];
           end
      endcase

    end else if (cbd_pos < cbd_size) begin
      current_instruction_read_from <= cbd_base+cbd_pos;
      command_valid_read            <= 1;
      cbd_pos                       <= cbd_pos + 1;

    end else begin
      `onread(cbd_r, cbd_a)
        cbd_pos       <= 0;
        cbd_size      <= cbd_d[(`CODEBAG_SIZE_BITS-1):0];
        cbd_base      <= cbd_d[(`INSTRUCTION_WIDTH-1):(`CODEBAG_SIZE_BITS)];

      end else begin
        `onread(preload_r, preload_a)
          if (preload_size == 0) begin
            preload_size     <= preload_d;
          end else if (!launched) begin
            write_flag <= 1;
            write_data <= preload_d;
            in_addr <= preload_pos;
            if (preload_pos == 0) begin
              temp_base = preload_d[(`INSTRUCTION_WIDTH-(3+`DESTINATION_ADDRESS_BITS)):(`CODEBAG_SIZE_BITS)];
              temp_size = preload_d[(`CODEBAG_SIZE_BITS-1):0];
            end
            if ((preload_pos+1) == preload_size) begin
              cbd_pos  <= 0;
              cbd_base <= temp_base;
              cbd_size <= temp_size;
              launched <= 1;
            end
            preload_pos      <= preload_pos + 1;
          end
        end
      end
    end
  end
endmodule

  



== Test ==============================================================
// expected output
#expect 12
#expect 13
#expect 14

// ships required in order to run this code
#ship debug          : Debug
#ship memory         : Memory

// instructions not in any codebag are part of the "root codebag"
// which is dispatched when the code is loaded

BOB:              sendto memory.inCBD;
memory.inCBD:     [*] take, deliver;
debug.in:         [*] take, deliver;


// This codebag illustrates how to do a loop.  Notice that this
// is actually an uncontrolled data emitter -- it could clog the
//  switch fabric!

BOB: {
  12:           sendto debug.in;
  13:           sendto debug.in;
  14:           sendto debug.in;
}


== Constants ========================================================
== TeX ==============================================================
\begin{verbatim}
TODO: count/stride
TODO: multiple interfaces to a single memory
\end{verbatim}

== Contributors =========================================================
Adam Megacz <megacz@cs.berkeley.edu>