module main
 (sys_clk_pin,   /* I think this is 100Mhz */
  sys_rst_pin,
  fpga_0_RS232_Uart_1_ctsN_pin,
  fpga_0_RS232_Uart_1_rtsN_pin,
  fpga_0_RS232_Uart_1_sin_pin,
  fpga_0_RS232_Uart_1_sout_pin
 );

  input  sys_clk_pin;
  input  sys_rst_pin;
  input  fpga_0_RS232_Uart_1_ctsN_pin;
  output fpga_0_RS232_Uart_1_rtsN_pin;
  input  fpga_0_RS232_Uart_1_sin_pin;
  output fpga_0_RS232_Uart_1_sout_pin;

  wire clk;
  assign clk = sys_clk_pin;
  wire break;
  wire rst;
  assign rst = sys_rst_pin;

  wire       data_to_host_full;
  wire       data_to_host_write_enable;
  wire [7:0] data_to_host;

  wire       data_to_fleet_empty;
  wire       data_to_fleet_read_enable;
  wire [7:0] data_to_fleet;

  reg we;
  reg re;
  reg [7:0] data_to_host_r;

  wire ser_rst;
  reg ser_rst_r;
  initial ser_rst_r = 0;
  assign ser_rst = rst & ser_rst_r;

  wire sio_ce;
  wire sio_ce_x4;
  sasc_brg sasc_brg(clk, ser_rst, 10, 217, sio_ce, sio_ce_x4);
  sasc_top sasc_top(clk, ser_rst,
                    fpga_0_RS232_Uart_1_sin_pin,
                    fpga_0_RS232_Uart_1_sout_pin,
                    fpga_0_RS232_Uart_1_ctsN_pin,
                    fpga_0_RS232_Uart_1_rtsN_pin, 
                    sio_ce,
                    sio_ce_x4,
                    data_to_host,
                    data_to_fleet,
                    data_to_fleet_read_enable,
                    data_to_host_write_enable,
                    data_to_host_full,
                    data_to_fleet_empty,
                    break);

   reg data_to_host_write_enable_reg;
   reg data_to_fleet_read_enable_reg;

   reg root_out_a_reg;
   reg root_in_r_reg;
   reg [7:0] root_in_d_reg;
   wire root_in_a;
   wire root_in_r;
   wire root_out_a;
   wire root_out_r;
   wire [7:0] root_in_d;


   root my_root(clk, rst && !break, 
                root_in_r,  root_in_a,  root_in_d,
                root_out_r, root_out_a, data_to_host);
/*
   fifo4 my_root(clk, rst,
                root_in_r,  root_in_a,  root_in_d,
                root_out_r, root_out_a, data_to_host);
*/
   assign root_out_a                = root_out_a_reg;                
   assign root_in_r                 = root_in_r_reg;
   assign data_to_fleet_read_enable = data_to_fleet_read_enable_reg;
   assign data_to_host_write_enable = data_to_host_write_enable_reg;
   assign root_in_d                 = root_in_d_reg;

   // fpga -> host
   always @(posedge clk)
   begin
     data_to_host_write_enable_reg = 0;
     if (root_out_r && !root_out_a_reg && !data_to_host_full) begin
       data_to_host_write_enable_reg = 1;
       root_out_a_reg = 1;
     end else if (root_out_a_reg && !root_out_r) begin
       root_out_a_reg = 0;
     end
   end

   // host -> fpga
   always @(posedge clk)
   begin
     ser_rst_r <= 1;
     data_to_fleet_read_enable_reg = 0;
     if (!data_to_fleet_empty && !root_in_r_reg && !root_in_a) begin
        root_in_r_reg = 1;
        root_in_d_reg = data_to_fleet;
        data_to_fleet_read_enable_reg = 1;
     end else begin
        if (root_in_a) begin
          root_in_r_reg = 0;
        end
     end
   end

   initial
   begin
     root_in_r_reg = 0;
     root_in_d_reg = 0;
     root_out_a_reg = 0;
     data_to_fleet_read_enable_reg = 0;
     data_to_host_write_enable_reg = 0;
   end
endmodule