module main (sys_clk_pin, /* 100Mhz */ sys_rst_pin, fpga_0_RS232_Uart_1_ctsN_pin, fpga_0_RS232_Uart_1_rtsN_pin, fpga_0_RS232_Uart_1_sin_pin, fpga_0_RS232_Uart_1_sout_pin, ddr1_Clk_pin, ddr1_Clk_n_pin, ddr1_Addr_pin, ddr1_BankAddr_pin, ddr1_CAS_n_pin, ddr1_CE_pin, ddr1_CS_n_pin, ddr1_RAS_n_pin, ddr1_WE_n_pin, ddr1_DM_pin, ddr1_DQS, ddr1_DQ, ddr2_ODT_pin, ddr2_Clk_pin, ddr2_Clk_n_pin, ddr2_Addr_pin, ddr2_BankAddr_pin, ddr2_CAS_n_pin, ddr2_CE_pin, ddr2_CS_n_pin, ddr2_RAS_n_pin, ddr2_WE_n_pin, ddr2_DM_pin, ddr2_DQS, ddr2_DQS_n, ddr2_DQ, vga_psave, vga_hsync, vga_vsync, vga_sync, vga_blank, vga_r, vga_g, vga_b, vga_clkout, fpga_0_LEDs_8Bit_GPIO_IO_pin ); input sys_clk_pin; input sys_rst_pin; input fpga_0_RS232_Uart_1_ctsN_pin; output fpga_0_RS232_Uart_1_rtsN_pin; input fpga_0_RS232_Uart_1_sin_pin; output fpga_0_RS232_Uart_1_sout_pin; output ddr1_Clk_pin; output ddr1_Clk_n_pin; output [12:0] ddr1_Addr_pin; output [1:0] ddr1_BankAddr_pin; output ddr1_CAS_n_pin; output ddr1_CE_pin; output ddr1_CS_n_pin; output ddr1_RAS_n_pin; output ddr1_WE_n_pin; output [3:0] ddr1_DM_pin; inout [3:0] ddr1_DQS; inout [31:0] ddr1_DQ; output ddr2_ODT_pin; output ddr2_Clk_pin; output ddr2_Clk_n_pin; output [12:0] ddr2_Addr_pin; output [1:0] ddr2_BankAddr_pin; output ddr2_CAS_n_pin; output ddr2_CE_pin; output ddr2_CS_n_pin; output ddr2_RAS_n_pin; output ddr2_WE_n_pin; output [7:0] ddr2_DM_pin; inout [7:0] ddr2_DQS; inout [7:0] ddr2_DQS_n; inout [63:0] ddr2_DQ; wire [31:0] dram_addr; wire dram_addr_r; wire dram_addr_a; wire dram_isread; wire [63:0] dram_write_data; wire dram_write_data_push; wire dram_write_data_full; wire [63:0] dram_read_data; wire dram_read_data_pop; wire dram_read_data_empty; wire [1:0] dram_read_data_latency; wire [31:0] ddr2_addr; wire ddr2_addr_r; wire ddr2_addr_a; wire ddr2_isread; wire [63:0] ddr2_write_data; wire ddr2_write_data_push; wire ddr2_write_data_full; wire [63:0] ddr2_read_data; wire ddr2_read_data_pop; wire ddr2_read_data_empty; wire [1:0] ddr2_read_data_latency; output vga_psave; output vga_hsync; output vga_vsync; output vga_sync; output vga_blank; output [7:0] vga_r; output [7:0] vga_g; output [7:0] vga_b; output vga_clkout; wire clk; wire clk_fb; wire clk50mhz; wire clk_unbuffered; wire vga_clk; wire vga_clk_fb; wire vga_clk_unbuffered; output [7:0] fpga_0_LEDs_8Bit_GPIO_IO_pin; wire [7:0] leds; assign fpga_0_LEDs_8Bit_GPIO_IO_pin = ~leds; assign leds[5:0] = dram_read_data[5:0]; assign leds[6] = dram_addr_r; assign leds[7] = dram_addr_a; //assign clk = sys_clk_pin; /* reg clk_unbuffered; initial clk_unbuffered = 0; always @(posedge sys_clk_pin) begin clk_unbuffered = ~clk_unbuffered; end assign clk_unbuffered = sys_clk_pin; */ BUFG GBUF_FOR_MUX_CLOCK (.I(clk_unbuffered), .O(clk)); DCM #( .CLKFX_MULTIPLY(4), .CLKFX_DIVIDE(8), .CLKIN_PERIOD("10 ns") ) mydcm( .CLKIN (sys_clk_pin), .CLKFB(clk_fb), .CLKFX (clk_unbuffered), .CLK0 (clk_fb) ); BUFG GBUF_FOR_VGA_CLOCK (.I(vga_clk_unbuffered), .O(vga_clk)); DCM // 25Mhz VGA clock #( .CLKFX_MULTIPLY(4), .CLKFX_DIVIDE(16), .CLKIN_PERIOD("20 ns") ) vgadcm ( .CLKIN (clk_unbuffered), .CLKFB(vga_clk_fb), .CLKFX (vga_clk_unbuffered), .CLK0 (vga_clk_fb) ); wire break_o; wire break; reg break_last; reg send_k; initial send_k = 0; wire rst; assign rst = sys_rst_pin; wire data_to_host_full; wire data_to_host_write_enable; wire [7:0] data_to_host; wire data_to_fleet_empty; wire data_to_fleet_read_enable; wire [7:0] data_to_fleet; reg we; reg re; reg [7:0] data_to_host_r; assign data_to_host = data_to_host_r; wire ser_rst; reg ser_rst_r; initial ser_rst_r = 0; assign ser_rst = (rst & ser_rst_r); wire sio_ce; wire sio_ce_x4; //sasc_brg sasc_brg(clk, ser_rst, 8, 65, sio_ce, sio_ce_x4); // sasc_brg sasc_brg(clk, ser_rst, 3, 65, sio_ce, sio_ce_x4); sasc_brg sasc_brg(sys_clk_pin, ser_rst, 8, 65, sio_ce, sio_ce_x4); sasc_top sasc_top(clk, ser_rst, fpga_0_RS232_Uart_1_sin_pin, fpga_0_RS232_Uart_1_sout_pin, fpga_0_RS232_Uart_1_ctsN_pin, fpga_0_RS232_Uart_1_rtsN_pin, sio_ce, sio_ce_x4, data_to_host, data_to_fleet, data_to_fleet_read_enable, data_to_host_write_enable, data_to_host_full, data_to_fleet_empty, break_o, break); // break and break_o are _active high_ always @(posedge clk) break_last <= break_o; assign break = break_o && !break_last; assign break_done = !break_o && break_last; reg data_to_host_write_enable_reg; reg data_to_fleet_read_enable_reg; reg root_out_a_reg; reg root_in_r_reg; reg [7:0] root_in_d_reg; wire root_in_a; wire root_in_r; wire root_out_a; wire root_out_r; wire [7:0] root_in_d; wire [7:0] root_out_d; /* * There is some very weird timing thing going on here; we need to * hold reset low for more than one clock in order for it to propagate * all the way to the docks. */ root my_root(clk, rst && !break_o, root_in_r, root_in_a, root_in_d, root_out_r, root_out_a, root_out_d, dram_addr, dram_addr_r, dram_addr_a, dram_isread, dram_write_data, dram_write_data_push, dram_write_data_full, dram_read_data, dram_read_data_pop, dram_read_data_empty, dram_read_data_latency, vga_clk, vga_psave, vga_hsync, vga_vsync, vga_sync, vga_blank, vga_r, vga_g, vga_b, vga_clkout ); /* fifo4 my_root(clk, rst, root_in_r, root_in_a, root_in_d, root_out_r, root_out_a, data_to_host); */ assign root_out_a = root_out_a_reg; assign root_in_r = root_in_r_reg; assign data_to_fleet_read_enable = data_to_fleet_read_enable_reg; assign data_to_host_write_enable = data_to_host_write_enable_reg; assign root_in_d = root_in_d_reg; // fpga -> host always @(posedge clk) begin if (break) begin root_out_a_reg = 0; data_to_host_write_enable_reg <= 0; end else if (break_done) begin data_to_host_write_enable_reg <= 1; data_to_host_r <= 111; send_k <= 1; end else if (send_k) begin data_to_host_write_enable_reg <= 1; data_to_host_r <= 107; send_k <= 0; end else if (root_out_r && !root_out_a_reg && !data_to_host_full) begin data_to_host_write_enable_reg <= 1; data_to_host_r <= root_out_d; root_out_a_reg = 1; end else if (root_out_a_reg && !root_out_r) begin data_to_host_write_enable_reg <= 0; root_out_a_reg = 0; end else begin data_to_host_write_enable_reg <= 0; end end // host -> fpga always @(posedge clk) begin ser_rst_r <= 1; if (break) begin root_in_r_reg <= 0; root_in_d_reg <= 0; data_to_fleet_read_enable_reg <= 0; end else if (!data_to_fleet_empty && !root_in_r_reg && !root_in_a) begin root_in_r_reg <= 1; root_in_d_reg <= data_to_fleet; data_to_fleet_read_enable_reg <= 1; end else begin data_to_fleet_read_enable_reg <= 0; if (root_in_a) begin root_in_r_reg <= 0; end end end initial begin root_in_r_reg = 0; root_in_d_reg = 0; root_out_a_reg = 0; data_to_fleet_read_enable_reg = 0; data_to_host_write_enable_reg = 0; end ddr_ctrl #( .clk_freq( 50000000 ), .clk_multiply( 12 ), .clk_divide( 5 ), .phase_shift( 0 ), .wait200_init( 26 ) ) ddr_ctrl ( .ddr_a( ddr1_Addr_pin ), .ddr_clk( ddr1_Clk_pin ), .ddr_clk_n( ddr1_Clk_n_pin ), .ddr_ba( ddr1_BankAddr_pin ), .ddr_dq( ddr1_DQ ), .ddr_dm( ddr1_DM_pin ), .ddr_dqs( ddr1_DQS ), .ddr_cs_n( ddr1_CS_n_pin ), .ddr_ras_n( ddr1_RAS_n_pin ), .ddr_cas_n( ddr1_CAS_n_pin ), .ddr_we_n( ddr1_WE_n_pin ), .ddr_cke( ddr1_CE_pin ), .clk(clk), .reset(!rst), .rot(3'b100), .fml_wr(!dram_isread && dram_addr_r), .fml_done(dram_addr_a), .fml_rd( dram_isread && dram_addr_r), .fml_adr(dram_addr), .fml_din(dram_write_data), .fml_dout(dram_read_data), // .fml_msk(16'hffff) .fml_msk(16'h0) ); /* ddr2spa #( // fabtech : integer := virtex4; // memtech : integer := 0; // rskew : integer := 0; // hindex : integer := 0; // haddr : integer := 0; // hmask : integer := 16#f00#; // ioaddr : integer := 16#000#; // iomask : integer := 16#fff#; .mhz(100), .clkmul(2), .clkdiv(1), // col : integer := 9; // Mbyte : integer := 16; // rstdel : integer := 200; .pwron(1), //oepol : integer := 0; .ddrbits(64), .ahbfreq(50), //readdly : integer := 1; -- 1 added read latency cycle //ddelayb0 : integer := 0; -- Data delay value (0 - 63) //ddelayb1 : integer := 0; -- Data delay value (0 - 63) //ddelayb2 : integer := 0; -- Data delay value (0 - 63) //ddelayb3 : integer := 0; -- Data delay value (0 - 63) //ddelayb4 : integer := 0; -- Data delay value (0 - 63) //ddelayb5 : integer := 0; -- Data delay value (0 - 63) //ddelayb6 : integer := 0; -- Data delay value (0 - 63) //ddelayb7 : integer := 0; -- Data delay value (0 - 63) //numidelctrl : integer := 4; .norefclk(1) //odten : integer := 0 ) ddr2_spa ( .rst_ddr(sys_rst_pin), .rst_ahb(rst), .clk_ddr(sys_clk_pin), .clk_ahb(clk), //clkref200 : in std_logic; //lock : out std_ulogic; -- DCM locked .clkddro(ddr2_clock), .clkddri(ddr2_clock), //ahbsi : in ahb_slv_in_type; //ahbso : out ahb_slv_out_type; .ddr_clk(ddr2_Clk_pin), .ddr_clkb(ddr2_Clk_n_pin), .ddr_cke(ddr2_CE_pin), .ddr_csb(ddr2_CS_n_pin), .ddr_web(ddr2_WE_n_pin), .ddr_rasb(ddr2_RAS_n_pin), .ddr_casb(ddr2_CAS_n_pin), .ddr_dm(ddr2_DM_pin), .ddr_dqs(ddr2_DQS), .ddr_dqsn(ddr2_DQS_n), .ddr_ad(ddr2_Addr_pin), .ddr_ba(ddr2_BankAddr_pin), .ddr_dq(ddr2_DQ), .ddr_odt(ddr2_ODT_pin) ); */ endmodule