module `MODULE_NAME(clk, rst, 
               in_r, in_a_, in_d,
               out_r_, out_a, out_d_); 
    input  clk;
    input  rst; 
    input  in_r;
    output in_a_;
    output out_r_;
    input  out_a;
    input  [(`WIDTH-1):0] in_d;
    output [(`WIDTH-1):0] out_d_;

    reg in_a;
    reg out_r;
    assign in_a_ = in_a;
    assign out_r_ = out_r;

    wire[((1<<(`ADDR_BITS))-1):0] controlx;
    reg[((1<<(`ADDR_BITS))-1):0] control;
    initial control = 0;

    genvar i;
    generate
      if (`ADDR_BITS > 1) begin: OUT
      for(i=1; i<=((1<<`ADDR_BITS)-2) ; i=i+1) begin : OUT
        assign controlx[i] =
           ( control[i-1] && !control[i]                 ) ? 1 :
           (                  control[i] && !control[i+1]) ? 0 :
           control[i];
      end
      end
    endgenerate

    reg[3:0] addr;
    initial  addr = 4'b1111;

    reg inchead;
    reg inctail;
    reg[3:0] count;

    genvar j;
    generate
      for(j=0; j<`WIDTH ; j=j+1) begin : OUTX
         SRL16E SRL16E (.Q (out_d_[j]),
                        .A0 (addr[0]),
                        .A1 (addr[1]),
                        .A2 (addr[2]),
                        .A3 (addr[3]),
                        .CE (in_r && !in_a && !control[0] && count==0),
                        .CLK (clk),
                        .D (in_d[j]));
         defparam SRL16E.INIT = 0;
      end
    endgenerate

    assign controlx[(1<<`ADDR_BITS)-1] =
        !control[(1<<`ADDR_BITS)-1] ? control[(1<<`ADDR_BITS)-2] : (!out_r && !out_a) ? 0 : control[(1<<`ADDR_BITS)-1];

    always @(posedge clk) begin 
        if (rst) begin
          out_r <= 0;
          in_a <= 0;
          control <= 0;
          addr <= 4'b1111;

        end else if (count!=0) begin
          count <= count-1;

        end else begin

          count <= `DELAY;

          inchead = 0;
          inctail = 0;
          if (!in_r && in_a) in_a <= 0;
          if (control[0]) begin
             if (!control[1]) control[0] <= 0;
          end else if (in_r && !in_a) begin
            control[0] <= 1;
            inctail = 1;
            in_a <= 1;
          end
  
          control[(1<<`ADDR_BITS)-1:1] <= controlx[(1<<`ADDR_BITS)-1:1];
  
          if (control[(1<<`ADDR_BITS)-1] && !out_r && !out_a) begin
            out_r <= 1;
          end
          if (out_r && out_a) begin
            out_r <= 0;
            inchead = 1;
          end
          if (          inchead && !inctail) begin
            addr <= addr-1;
          end else if (!inchead &&  inctail) begin
            addr <= addr+1;
          end
      end
    end
endmodule