module fifo4(clk
    , in_r, in_a_, in
    , out_r_, out_a, out_
   );

    input clk;
    wire fifostage_3_in_a;
wire fifostage_3_in_r;
wire   [47:0]fifostage_3_in;

    output out_r_;
input out_a;
output [47:0]out_;
wire out_r;
wire   [47:0]out;

    wire fifostage_0_out_r;
wire [47:0]fifostage_0_out;
wire fifostage_0_out_a;

    wire fifostage_2_out_r;
wire [47:0]fifostage_2_out;
wire fifostage_2_out_a;

    wire fifostage_1_in_a;
wire fifostage_1_in_r;
wire   [47:0]fifostage_1_in;

    wire fifostage_0_in_a;
wire fifostage_0_in_r;
wire   [47:0]fifostage_0_in;

    wire fifostage_1_out_r;
wire [47:0]fifostage_1_out;
wire fifostage_1_out_a;

    wire fifostage_3_out_r;
wire [47:0]fifostage_3_out;
wire fifostage_3_out_a;

    input in_r;
output in_a_;
input [47:0]in;
wire in_a;

    wire fifostage_2_in_a;
wire fifostage_2_in_r;
wire   [47:0]fifostage_2_in;

    
    assign out_r_ = out_r;
assign out_ = out;

    assign fifostage_1_in_r = fifostage_0_out_r;
assign fifostage_0_out_a = fifostage_1_in_a;
assign fifostage_1_in   = fifostage_0_out;

    assign fifostage_3_in_r = fifostage_2_out_r;
assign fifostage_2_out_a = fifostage_3_in_a;
assign fifostage_3_in   = fifostage_2_out;

    
    
    assign fifostage_2_in_r = fifostage_1_out_r;
assign fifostage_1_out_a = fifostage_2_in_a;
assign fifostage_2_in   = fifostage_1_out;

    assign out_r = fifostage_3_out_r;
assign fifostage_3_out_a = out_a;
assign out   = fifostage_3_out;

    assign in_a_ = in_a;
assign fifostage_0_in_r = in_r;
assign in_a = fifostage_0_in_a;
assign fifostage_0_in   = in;

    
  fifostage fifostage_1(clk
, fifostage_1_in_r, fifostage_1_in_a, fifostage_1_in
, fifostage_1_out_r, fifostage_1_out_a, fifostage_1_out
   );
  fifostage fifostage_2(clk
, fifostage_2_in_r, fifostage_2_in_a, fifostage_2_in
, fifostage_2_out_r, fifostage_2_out_a, fifostage_2_out
   );
  fifostage fifostage_0(clk
, fifostage_0_in_r, fifostage_0_in_a, fifostage_0_in
, fifostage_0_out_r, fifostage_0_out_a, fifostage_0_out
   );
  fifostage fifostage_3(clk
, fifostage_3_in_r, fifostage_3_in_a, fifostage_3_in
, fifostage_3_out_r, fifostage_3_out_a, fifostage_3_out
   );
always @(posedge clk) begin
 begin end
end
endmodule