`include "macros.v"

module fifostage (clk, 
                      in_r,   in_a_, in_d,
                      out_r_, out_a, out_d_);

  input  clk;
  `input( in_r,   in_a,   in_a_, [(`PACKET_WIDTH-1):0], in_d)
  `output(out_r,  out_r_, out_a, [(`PACKET_WIDTH-1):0], out_d_)
  `defreg(out_d_,                [(`PACKET_WIDTH-1):0], out_d)

  reg full;

  always @(posedge clk) begin
    if (!full) begin
      `onread(in_r, in_a)
        out_d = in_d;
        full = 1;
      end
    end else begin
      `onwrite(out_r, out_a)
        full = 0;
      end
    end
  end

endmodule