(clk,
            in_r,  in_a_, in_d,
            out0_r_, out0_a,  out0_d_,
            out1_r_, out1_a,  out1_d_);

  input                  clk;
  reg                    full;
  reg                    dir;
  initial                full=0;

  `input(in_r,    in_a,    in_a_,   [`XWIDTH:0], in_d)
  `output(out0_r, out0_r_, out0_a,  [`XWIDTH:0], out0_d_)
  `output(out1_r, out1_r_, out1_a,  [`XWIDTH:0], out1_d_)
  `defreg(dat_, [`XWIDTH:0], dat)

  assign out0_d_ = dat_;
  assign out1_d_ = dat_;

  always @(posedge clk) begin
    if (full) begin
      if (dir==0) begin
        `onwrite(out0_r, out0_a)
          full = 0;
        end
      end else begin
        `onwrite(out1_r, out1_a)
          full = 0;
        end
      end
    end else begin
      `onread(in_r, in_a)
        full  = 1;
        dat   = in_d;
        dir   = `dest_steer(dat);
        `dest(dat) = `dest(dat) >> 1;
      end
    end
  end
   
endmodule