`include "macros.v"

module outbox(clk,
                  instr_r,       instr_a_,      instr_d,
                  fabric_in_r,   fabric_in_a_,  fabric_in_d,
                  fabric_out_r_, fabric_out_a,  fabric_out_d_,
                  ship_r,        ship_a_,       ship_d
                 );

  input clk;

  output fabric_in_a_;
  input  fabric_in_r;
  input  [(`DATAWIDTH-1):0] fabric_in_d;
  //`input(fabric_in_r,    fabric_in_a,   fabric_in_a_,   [(`DATAWIDTH-1):0],          fabric_in_d)
  `output(fabric_out_r,  fabric_out_r_, fabric_out_a,   [(`PACKET_WIDTH-1):0],       fabric_out_d_)
  `defreg(fabric_out_d_,                                [(`PACKET_WIDTH-1):0],       fabric_out_d)
  `input(ship_r,         ship_a,        ship_a_,        [(`DATAWIDTH-1):0],          ship_d)
  `input(instr_r,        instr_a,       instr_a_,       [(`INSTRUCTION_WIDTH-1):0],  instr_d)

  wire fabric_in_a0_;
  reg fabric_in_a0;
  assign fabric_in_a0_ = fabric_in_a0;

  `define token_in_r fabric_in_r0
  `define token_in_a fabric_in_a0
  `define token_in_d fabric_in_d0

  `define data_out_r fabric_out_r
  `define data_out_a fabric_out_a
  `define data_out_d fabric_out_d

  `define token_out_r fabric_out_r
  `define token_out_a fabric_out_a
  `define token_out_d fabric_out_d

  `define data_in_d ship_d
  `define data_in_a ship_a
  `define data_in_r ship_r

  wire  [(`PACKET_WIDTH-1):0] fabric_in_d0;

  fifo4 dfifo(clk, fabric_in_r,  fabric_in_a_,  fabric_in_d,
                   fabric_in_r0, fabric_in_a0_, fabric_in_d0);

  `define extra 
  `include "box.inc"
endmodule