********************** TSMC 90nm Header **************************

******************************************************************
* Set Process, Voltage and Temperature corner
******************************************************************

.protect
.lib '/import/async/cad/process/tsmc090/spice_models/models/cln90g_lk.l' TT
.lib '/import/async/cad/process/tsmc090/spice_models/models/cln90g_lk.l' TT_RES
.lib '/import/async/cad/process/tsmc090/spice_models/models/cln90g_lk.l' TT_18
.lib '/import/async/cad/process/tsmc090/spice_models/models/cln90g_lk.l' TT_na18
.lib '/import/async/cad/process/tsmc090/spice_models/models/cln90g_lk.l' TT_DIO_esd
.lib '/import/async/cad/process/tsmc090/spice_models/models/cln90g_lk.l' TT_DIO_18
.unprotect

.param sup=0.9    * Supply voltage
.temp 80          * Temperature

******************************************************************
* Standard Parameters and Options
******************************************************************

.param vsupply=sup
.param vhi=sup
.param vlo=0
.param strong0=0 * Used in verilog, just needs to be defined to run hspice
.param strong1=1 * Used in verilog, just needs to be defined to run hspice
vvdd vdd gnd 'sup'
.options ACCT OPTS post
*.option post probe
.opt scale=0.05u
.op

.param AVT0N = AGAUSS(0.0,  '0.01 / 0.1' , 1)
.param AVT0P = AGAUSS(0.0,  '0.01 / 0.1' , 1)
.param ABN = AGAUSS(0.0,  '0.02 / 0.1' , 1)
.param ABP = AGAUSS(0.0,  '0.02 / 0.1' , 1)

******************************************************************
* hsim gunk
******************************************************************
.hsimparam HSIMDCINIT=0
.hsimparam HSIMVDD=0.9
.param HSIMSTOPAT=0
.param HSIMOUTPUT=fsdb 
.param HSIMOUTPUTTBL=rawfile