// output ///////////////////////////////////////////////////////////////////
#skip
#expect 14
#expect 13
#expect 12
#expect 11

// program //////////////////////////////////////////////////////////////////
#ship debug        : Debug
#ship memory       : Memory
#ship fifo         : Fifo

// dumb configurations
debug.in:        set ilc=*;  recv, deliver;
memory.inAddrRead:   set ilc=*;  recv, deliver;
memory.inAddrWrite:   set ilc=*;  recv, deliver;
memory.inDataWrite:   set ilc=*;  recv, deliver;
//memory.inCount:  set ilc=*;  recv, deliver;
//memory.inStride: set ilc=*;  recv, deliver;
fifo.in:         set ilc=*;  recv, deliver;

// addresses and values to initialize the memory with
//1:  send to memory.inAddrWrite;
//4:  send to memory.inCount;
//1:  send to memory.inStride;
//11: send to memory.inDataWrite;
//12: send to memory.inDataWrite;
//13: send to memory.inDataWrite;
//14: send to memory.inDataWrite;

// send write-completion tokens to the fifo output
memory.out:
  set ilc=4; collect, send token to fifo.out;
  set ilc=*;  collect, send to debug.in;

// when the write-completion tokens accumulate, unleash
// the read addresses
fifo.out:
  set ilc=4; recv token;
  collect, send to memory.inAddrRead;

// read addresses
//4: send to fifo.in;
//4: send to memory.inCount;
//-1: send to memory.inStride;