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Add count of reg-reg moves remaining for linear allocator stats
[ghc-hetmet.git]
/
compiler
/
nativeGen
/
MachInstrs.hs
diff --git
a/compiler/nativeGen/MachInstrs.hs
b/compiler/nativeGen/MachInstrs.hs
index
baac1cd
..
0c5dbdd
100644
(file)
--- a/
compiler/nativeGen/MachInstrs.hs
+++ b/
compiler/nativeGen/MachInstrs.hs
@@
-15,7
+15,9
@@
module MachInstrs (
-- * Machine instructions
Instr(..),
Cond(..), condUnsigned, condToSigned, condToUnsigned,
-- * Machine instructions
Instr(..),
Cond(..), condUnsigned, condToSigned, condToUnsigned,
-
+#if powerpc_TARGET_ARCH
+ condNegate,
+#endif
#if !powerpc_TARGET_ARCH && !i386_TARGET_ARCH && !x86_64_TARGET_ARCH
Size(..), machRepSize,
#endif
#if !powerpc_TARGET_ARCH && !i386_TARGET_ARCH && !x86_64_TARGET_ARCH
Size(..), machRepSize,
#endif
@@
-50,8
+52,8
@@
import GHC.Exts
-- Our flavours of the Cmm types
-- Type synonyms for Cmm populated with native code
-- Our flavours of the Cmm types
-- Type synonyms for Cmm populated with native code
-type NatCmm = GenCmm CmmStatic Instr
-type NatCmmTop = GenCmmTop CmmStatic Instr
+type NatCmm = GenCmm CmmStatic [CmmStatic] Instr
+type NatCmmTop = GenCmmTop CmmStatic [CmmStatic] Instr
type NatBasicBlock = GenBasicBlock Instr
-- -----------------------------------------------------------------------------
type NatBasicBlock = GenBasicBlock Instr
-- -----------------------------------------------------------------------------
@@
-140,6
+142,20
@@
condToUnsigned GE = GEU
condToUnsigned LE = LEU
condToUnsigned x = x
condToUnsigned LE = LEU
condToUnsigned x = x
+#if powerpc_TARGET_ARCH
+condNegate ALWAYS = panic "condNegate: ALWAYS"
+condNegate EQQ = NE
+condNegate GE = LTT
+condNegate GEU = LU
+condNegate GTT = LE
+condNegate GU = LEU
+condNegate LE = GTT
+condNegate LEU = GU
+condNegate LTT = GE
+condNegate LU = GEU
+condNegate NE = EQQ
+#endif
+
-- -----------------------------------------------------------------------------
-- Sizes on this architecture
-- -----------------------------------------------------------------------------
-- Sizes on this architecture
@@
-210,6
+226,9
@@
data Instr
| DELTA Int -- specify current stack offset for
-- benefit of subsequent passes
| DELTA Int -- specify current stack offset for
-- benefit of subsequent passes
+ | SPILL Reg Int -- ^ spill this reg to a stack slot
+ | RELOAD Int Reg -- ^ reload this reg from a stack slot
+
-- -----------------------------------------------------------------------------
-- Alpha instructions
-- -----------------------------------------------------------------------------
-- Alpha instructions
@@
-472,8
+491,8
@@
bit or 64 bit precision.
| CVTSS2SD Reg Reg -- F32 to F64
| CVTSD2SS Reg Reg -- F64 to F32
| CVTSS2SD Reg Reg -- F32 to F64
| CVTSD2SS Reg Reg -- F64 to F32
- | CVTSS2SI Operand Reg -- F32 to I32/I64 (with rounding)
- | CVTSD2SI Operand Reg -- F64 to I32/I64 (with rounding)
+ | CVTTSS2SIQ Operand Reg -- F32 to I32/I64 (with truncation)
+ | CVTTSD2SIQ Operand Reg -- F64 to I32/I64 (with truncation)
| CVTSI2SS Operand Reg -- I32/I64 to F32
| CVTSI2SD Operand Reg -- I32/I64 to F64
| CVTSI2SS Operand Reg -- I32/I64 to F32
| CVTSI2SD Operand Reg -- I32/I64 to F64
@@
-504,6
+523,7
@@
bit or 64 bit precision.
-- Jumping around.
| JMP Operand
| JXX Cond BlockId -- includes unconditional branches
-- Jumping around.
| JMP Operand
| JXX Cond BlockId -- includes unconditional branches
+ | JXX_GBL Cond Imm -- non-local version of JXX
| JMP_TBL Operand [BlockId] -- table jump
| CALL (Either Imm Reg) [Reg]
| JMP_TBL Operand [BlockId] -- table jump
| CALL (Either Imm Reg) [Reg]
@@
-660,6
+680,7
@@
fPair other = pprPanic "fPair(sparc NCG)" (ppr other)
| CMPL MachRep Reg RI --- size, src1, src2
| BCC Cond BlockId
| CMPL MachRep Reg RI --- size, src1, src2
| BCC Cond BlockId
+ | BCCFAR Cond BlockId
| JMP CLabel -- same as branch,
-- but with CLabel instead of block ID
| MTCTR Reg
| JMP CLabel -- same as branch,
-- but with CLabel instead of block ID
| MTCTR Reg
@@
-719,4
+740,5
@@
fPair other = pprPanic "fPair(sparc NCG)" (ppr other)
| FETCHPC Reg -- pseudo-instruction:
-- bcl to next insn, mflr reg
| FETCHPC Reg -- pseudo-instruction:
-- bcl to next insn, mflr reg
+ | LWSYNC -- memory barrier
#endif /* powerpc_TARGET_ARCH */
#endif /* powerpc_TARGET_ARCH */