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NCG: Rename MachRegs, MachInstrs -> Regs, Instrs to reflect arch specific naming
[ghc-hetmet.git]
/
compiler
/
nativeGen
/
RegAlloc
/
Linear
/
Base.hs
diff --git
a/compiler/nativeGen/RegAlloc/Linear/Base.hs
b/compiler/nativeGen/RegAlloc/Linear/Base.hs
index
95c9965
..
ebd3107
100644
(file)
--- a/
compiler/nativeGen/RegAlloc/Linear/Base.hs
+++ b/
compiler/nativeGen/RegAlloc/Linear/Base.hs
@@
-3,7
+3,9
@@
module RegAlloc.Linear.Base (
BlockAssignment,
module RegAlloc.Linear.Base (
BlockAssignment,
+
Loc(..),
Loc(..),
+ regsOfLoc,
-- for stats
SpillReason(..),
-- for stats
SpillReason(..),
@@
-20,7
+22,7
@@
import RegAlloc.Linear.FreeRegs
import RegAlloc.Linear.StackMap
import RegLiveness
import RegAlloc.Linear.StackMap
import RegLiveness
-import MachRegs
+import Regs
import Outputable
import Unique
import Outputable
import Unique
@@
-65,6
+67,13
@@
instance Outputable Loc where
ppr l = text (show l)
ppr l = text (show l)
+-- | Get the reg numbers stored in this Loc.
+regsOfLoc :: Loc -> [RegNo]
+regsOfLoc (InReg r) = [r]
+regsOfLoc (InBoth r _) = [r]
+regsOfLoc (InMem _) = []
+
+
-- | Reasons why instructions might be inserted by the spiller.
-- Used when generating stats for -ddrop-asm-stats.
--
-- | Reasons why instructions might be inserted by the spiller.
-- Used when generating stats for -ddrop-asm-stats.
--
@@
-96,9
+105,10
@@
data RegAllocStats
data RA_State
= RA_State
data RA_State
= RA_State
+ {
-- | the current mapping from basic blocks to
-- the register assignments at the beginning of that block.
-- | the current mapping from basic blocks to
-- the register assignments at the beginning of that block.
- { ra_blockassig :: BlockAssignment
+ ra_blockassig :: BlockAssignment
-- | free machine registers
, ra_freeregs :: {-#UNPACK#-}!FreeRegs
-- | free machine registers
, ra_freeregs :: {-#UNPACK#-}!FreeRegs