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Eliminate more dead reg->reg moves in linear allocator
[ghc-hetmet.git]
/
compiler
/
nativeGen
/
RegAllocColor.hs
diff --git
a/compiler/nativeGen/RegAllocColor.hs
b/compiler/nativeGen/RegAllocColor.hs
index
40e3bc3
..
9c21faa
100644
(file)
--- a/
compiler/nativeGen/RegAllocColor.hs
+++ b/
compiler/nativeGen/RegAllocColor.hs
@@
-50,12
+50,12
@@
maxSpinCount = 10
-- | The top level of the graph coloring register allocator.
--
regAlloc
-- | The top level of the graph coloring register allocator.
--
regAlloc
- :: UniqFM (UniqSet Reg) -- ^ the registers we can use for allocation
- -> UniqSet Int -- ^ the set of available spill slots.
- -> [LiveCmmTop] -- ^ code annotated with liveness information.
+ :: UniqFM (UniqSet Reg) -- ^ the registers we can use for allocation
+ -> UniqSet Int -- ^ the set of available spill slots.
+ -> [LiveCmmTop] -- ^ code annotated with liveness information.
-> UniqSM
-> UniqSM
- ( [NatCmmTop] -- ^ code with registers allocated.
- , [RegAllocStats] ) -- ^ stats for each stage of allocation
+ ( [NatCmmTop] -- ^ code with registers allocated.
+ , [RegAllocStats] ) -- ^ stats for each stage of allocation
regAlloc regsFree slotsFree code
= do
regAlloc regsFree slotsFree code
= do
@@
-63,7
+63,7
@@
regAlloc regsFree slotsFree code
<- regAlloc_spin 0 trivColorable regsFree slotsFree [] code
return ( code_final
<- regAlloc_spin 0 trivColorable regsFree slotsFree [] code
return ( code_final
- , debug_codeGraphs )
+ , reverse debug_codeGraphs )
regAlloc_spin (spinCount :: Int) triv regsFree slotsFree debug_codeGraphs code
= do
regAlloc_spin (spinCount :: Int) triv regsFree slotsFree debug_codeGraphs code
= do
@@
-79,11
+79,21
@@
regAlloc_spin (spinCount :: Int) triv regsFree slotsFree debug_codeGraphs code
-- build a conflict graph from the code.
graph <- buildGraph code
-- build a conflict graph from the code.
graph <- buildGraph code
- -- build a map of how many instructions each reg lives for
- -- this lazy, it won't be computed unless we need to spill
+ -- build a map of how many instructions each reg lives for.
+ -- this is lazy, it won't be computed unless we need to spill
let fmLife = plusUFMs_C (\(r1, l1) (r2, l2) -> (r1, l1 + l2))
$ map lifetimeCount code
let fmLife = plusUFMs_C (\(r1, l1) (r2, l2) -> (r1, l1 + l2))
$ map lifetimeCount code
+ -- record startup state
+ let stat1 =
+ if spinCount == 0
+ then Just $ RegAllocStatsStart
+ { raLiveCmm = code
+ , raGraph = graph
+ , raLifetimes = fmLife }
+ else Nothing
+
+
-- the function to choose regs to leave uncolored
let spill = chooseSpill_maxLife fmLife
-- the function to choose regs to leave uncolored
let spill = chooseSpill_maxLife fmLife
@@
-101,13
+111,11
@@
regAlloc_spin (spinCount :: Int) triv regsFree slotsFree debug_codeGraphs code
-- record what happened in this stage for debugging
let stat =
RegAllocStatsColored
-- record what happened in this stage for debugging
let stat =
RegAllocStatsColored
- { raLiveCmm = code
- , raGraph = graph_colored
- , raPatchedCmm = code_patched
- , raLifetimes = fmLife }
+ { raGraph = graph_colored
+ , raPatchedCmm = code_patched }
return ( code_nat
return ( code_nat
- , debug_codeGraphs ++ [stat]
+ , maybeToList stat1 ++ [stat] ++ debug_codeGraphs
, graph_colored)
else do
, graph_colored)
else do
@@
-122,14
+130,14
@@
regAlloc_spin (spinCount :: Int) triv regsFree slotsFree debug_codeGraphs code
-- record what happened in this stage for debugging
let stat =
RegAllocStatsSpill
-- record what happened in this stage for debugging
let stat =
RegAllocStatsSpill
- { raLiveCmm = code_spilled
- , raGraph = graph_colored
+ { raGraph = graph_colored
, raSpillStats = spillStats
, raSpillStats = spillStats
- , raLifetimes = fmLife }
+ , raLifetimes = fmLife
+ , raSpilled = code_spilled }
-- try again
regAlloc_spin (spinCount + 1) triv regsFree slotsFree'
-- try again
regAlloc_spin (spinCount + 1) triv regsFree slotsFree'
- (debug_codeGraphs ++ [stat])
+ (maybeToList stat1 ++ [stat] ++ debug_codeGraphs)
code_relive
code_relive
@@
-194,7
+202,7
@@
buildGraph code
-- | Add some conflict edges to the graph.
-- | Add some conflict edges to the graph.
--- Conflicts between virtual and real regs are recorded as exlusions.
+-- Conflicts between virtual and real regs are recorded as exclusions.
--
graphAddConflictSet
:: UniqSet Reg
--
graphAddConflictSet
:: UniqSet Reg
@@
-215,7
+223,7
@@
graphAddConflictSet set graph
in graph2
in graph2
--- | Add some coalesences edges to the graph
+-- | Add some coalesence edges to the graph
-- Coalesences between virtual and real regs are recorded as preferences.
--
graphAddCoalesce
-- Coalesences between virtual and real regs are recorded as preferences.
--
graphAddCoalesce