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Show spill/reload pseudo instrs in regalloc stage dump
[ghc-hetmet.git]
/
compiler
/
nativeGen
/
RegAllocColor.hs
diff --git
a/compiler/nativeGen/RegAllocColor.hs
b/compiler/nativeGen/RegAllocColor.hs
index
9c21faa
..
ecb5faf
100644
(file)
--- a/
compiler/nativeGen/RegAllocColor.hs
+++ b/
compiler/nativeGen/RegAllocColor.hs
@@
-106,16
+106,23
@@
regAlloc_spin (spinCount :: Int) triv regsFree slotsFree debug_codeGraphs code
then do
-- patch the registers using the info in the graph
let code_patched = map (patchRegsFromGraph graph_colored) code
then do
-- patch the registers using the info in the graph
let code_patched = map (patchRegsFromGraph graph_colored) code
+
+ -- strip off liveness information
let code_nat = map stripLive code_patched
let code_nat = map stripLive code_patched
+
+ -- rewrite SPILL/REALOAD pseudos into real instructions
+ let spillNatTop = mapGenBlockTop spillNatBlock
+ let code_final = map spillNatTop code_nat
-- record what happened in this stage for debugging
let stat =
RegAllocStatsColored
{ raGraph = graph_colored
-- record what happened in this stage for debugging
let stat =
RegAllocStatsColored
{ raGraph = graph_colored
- , raPatchedCmm = code_patched }
+ , raPatchedCmm = code_patched
+ , raFinalCmm = code_final }
return ( code_nat
return ( code_nat
- , maybeToList stat1 ++ [stat] ++ debug_codeGraphs
+ , [stat] ++ maybeToList stat1 ++ debug_codeGraphs
, graph_colored)
else do
, graph_colored)
else do
@@
-137,7
+144,7
@@
regAlloc_spin (spinCount :: Int) triv regsFree slotsFree debug_codeGraphs code
-- try again
regAlloc_spin (spinCount + 1) triv regsFree slotsFree'
-- try again
regAlloc_spin (spinCount + 1) triv regsFree slotsFree'
- (maybeToList stat1 ++ [stat] ++ debug_codeGraphs)
+ ([stat] ++ maybeToList stat1 ++ debug_codeGraphs)
code_relive
code_relive