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Fix a build error on powerpc/Linux; spotted by Jeroen Pulles
[ghc-hetmet.git]
/
compiler
/
nativeGen
/
RegAllocLinear.hs
diff --git
a/compiler/nativeGen/RegAllocLinear.hs
b/compiler/nativeGen/RegAllocLinear.hs
index
4b023c5
..
815bdfb
100644
(file)
--- a/
compiler/nativeGen/RegAllocLinear.hs
+++ b/
compiler/nativeGen/RegAllocLinear.hs
@@
-88,6
+88,7
@@
module RegAllocLinear (
#include "HsVersions.h"
#include "HsVersions.h"
+import BlockId
import MachRegs
import MachInstrs
import RegAllocInfo
import MachRegs
import MachInstrs
import RegAllocInfo
@@
-101,6
+102,7
@@
import UniqFM
import UniqSupply
import Outputable
import State
import UniqSupply
import Outputable
import State
+import FastString
import Data.Maybe
import Data.List
import Data.Maybe
import Data.List
@@
-574,7
+576,7
@@
saveClobberedTemps clobbered dying = do
recordSpill (SpillClobber temp)
let new_assign = addToUFM assig temp (InBoth reg slot)
recordSpill (SpillClobber temp)
let new_assign = addToUFM assig temp (InBoth reg slot)
- clobber new_assign (spill : COMMENT FSLIT("spill clobber") : instrs) rest
+ clobber new_assign (spill : COMMENT (fsLit "spill clobber") : instrs) rest
clobberRegs :: [RegNo] -> RegM ()
clobberRegs [] = return () -- common case
clobberRegs :: [RegNo] -> RegM ()
clobberRegs [] = return () -- common case
@@
-691,7
+693,7
@@
allocateRegsAndSpill reading keep spills alloc (r:rs) = do
(spill_insn, slot) <- spillR (RealReg my_reg) temp_to_push_out
let spill_store = (if reading then id else reverse)
(spill_insn, slot) <- spillR (RealReg my_reg) temp_to_push_out
let spill_store = (if reading then id else reverse)
- [ COMMENT FSLIT("spill alloc")
+ [ COMMENT (fsLit "spill alloc")
, spill_insn ]
-- record that this temp was spilled
, spill_insn ]
-- record that this temp was spilled
@@
-723,7
+725,7
@@
loadTemp True vreg (Just (InMem slot)) hreg spills
= do
insn <- loadR (RealReg hreg) slot
recordSpill (SpillLoad $ getUnique vreg)
= do
insn <- loadR (RealReg hreg) slot
recordSpill (SpillLoad $ getUnique vreg)
- return $ COMMENT FSLIT("spill load") : insn : spills
+ return $ COMMENT (fsLit "spill load") : insn : spills
loadTemp _ _ _ _ spills =
return spills
loadTemp _ _ _ _ spills =
return spills
@@
-807,7
+809,7
@@
joinToTargets block_live new_blocks instr (dest:dests) = do
joinToTargets block_live (block : new_blocks) instr' dests
joinToTargets block_live (block : new_blocks) instr' dests
--- | Construct a graph of register/spill movements.
+-- | Construct a graph of register\/spill movements.
--
-- We cut some corners by
-- a) not handling cyclic components
--
-- We cut some corners by
-- a) not handling cyclic components
@@
-825,7
+827,7
@@
makeRegMovementGraph adjusted_assig dest_assig
= expandNode vreg src
$ lookupWithDefaultUFM_Directly
dest_assig
= expandNode vreg src
$ lookupWithDefaultUFM_Directly
dest_assig
- (panic "RegisterAlloc.joinToTargets")
+ (panic "RegAllocLinear.makeRegMovementGraph")
vreg
in [ node | (vreg, src) <- ufmToList adjusted_assig
vreg
in [ node | (vreg, src) <- ufmToList adjusted_assig
@@
-908,7
+910,7
@@
handleComponent delta instr (CyclicSCC ((vreg, (InReg sreg),dsts):rest))
= do
restoreToReg <- loadR (RealReg reg) slot
moveInstr <- makeMove delta vreg r mem
= do
restoreToReg <- loadR (RealReg reg) slot
moveInstr <- makeMove delta vreg r mem
- return $ [COMMENT FSLIT("spill join move"), restoreToReg, moveInstr]
+ return $ [COMMENT (fsLit "spill join move"), restoreToReg, moveInstr]
getRestoreMoves [InReg reg] slot
= loadR (RealReg reg) slot >>= return . (:[])
getRestoreMoves [InReg reg] slot
= loadR (RealReg reg) slot >>= return . (:[])