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Implement SSE2 floating-point support in the x86 native code generator (#594)
[ghc-hetmet.git]
/
compiler
/
nativeGen
/
SPARC
/
Instr.hs
diff --git
a/compiler/nativeGen/SPARC/Instr.hs
b/compiler/nativeGen/SPARC/Instr.hs
index
5cb28d5
..
00b57f9
100644
(file)
--- a/
compiler/nativeGen/SPARC/Instr.hs
+++ b/
compiler/nativeGen/SPARC/Instr.hs
@@
-43,8
+43,6
@@
import FastString
import FastBool
import Outputable
import FastBool
import Outputable
-import GHC.Exts
-
-- | Register or immediate
data RI
-- | Register or immediate
data RI
@@
-375,6
+373,7
@@
sparc_mkSpillInstr reg _ slot
RcInteger -> II32
RcFloat -> FF32
RcDouble -> FF64
RcInteger -> II32
RcFloat -> FF32
RcDouble -> FF64
+ _ -> panic "sparc_mkSpillInstr"
in ST sz reg (fpRel (negate off_w))
in ST sz reg (fpRel (negate off_w))
@@
-393,6
+392,7
@@
sparc_mkLoadInstr reg _ slot
RcInteger -> II32
RcFloat -> FF32
RcDouble -> FF64
RcInteger -> II32
RcFloat -> FF32
RcDouble -> FF64
+ _ -> panic "sparc_mkLoadInstr"
in LD sz (fpRel (- off_w)) reg
in LD sz (fpRel (- off_w)) reg
@@
-440,6
+440,7
@@
sparc_mkRegRegMoveInstr src dst
RcInteger -> ADD False False src (RIReg g0) dst
RcDouble -> FMOV FF64 src dst
RcFloat -> FMOV FF32 src dst
RcInteger -> ADD False False src (RIReg g0) dst
RcDouble -> FMOV FF64 src dst
RcFloat -> FMOV FF32 src dst
+ _ -> panic "sparc_mkRegRegMoveInstr"
| otherwise
= panic "SPARC.Instr.mkRegRegMoveInstr: classes of src and dest not the same"
| otherwise
= panic "SPARC.Instr.mkRegRegMoveInstr: classes of src and dest not the same"