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[project @ 2004-08-13 10:45:16 by simonmar]
[ghc-hetmet.git]
/
ghc
/
compiler
/
nativeGen
/
MachMisc.lhs
diff --git
a/ghc/compiler/nativeGen/MachMisc.lhs
b/ghc/compiler/nativeGen/MachMisc.lhs
index
1d3c3ac
..
a641a8a
100644
(file)
--- a/
ghc/compiler/nativeGen/MachMisc.lhs
+++ b/
ghc/compiler/nativeGen/MachMisc.lhs
@@
-65,7
+65,7
@@
import FastString
import GLAEXTS
import TRACE ( trace )
import GLAEXTS
import TRACE ( trace )
-import Maybe ( catMaybes )
+import Maybes ( mapCatMaybes )
\end{code}
\begin{code}
\end{code}
\begin{code}
@@
-76,11
+76,11
@@
underscorePrefix = (cLeadingUnderscore == "YES")
fmtAsmLbl :: String -> String -- for formatting labels
fmtAsmLbl s
fmtAsmLbl :: String -> String -- for formatting labels
fmtAsmLbl s
- = IF_ARCH_alpha(
{- The alpha assembler likes temporary labels to look like $L123
instead of L123. (Don't toss the L, because then Lf28
turns into $f28.)
-}
{- The alpha assembler likes temporary labels to look like $L123
instead of L123. (Don't toss the L, because then Lf28
turns into $f28.)
-}
+ = IF_ARCH_alpha(
'$' : s
,{-otherwise-}
'.':'L':s
'$' : s
,{-otherwise-}
'.':'L':s
@@
-94,7
+94,8
@@
where do we start putting the rest of them?
\begin{code}
eXTRA_STK_ARGS_HERE :: Int
eXTRA_STK_ARGS_HERE
\begin{code}
eXTRA_STK_ARGS_HERE :: Int
eXTRA_STK_ARGS_HERE
- = IF_ARCH_alpha(0, IF_ARCH_i386(23{-6x4bytes-}, IF_ARCH_sparc(23, IF_ARCH_powerpc(24,???))))
+ = IF_ARCH_alpha(0, IF_ARCH_i386(23{-6x4bytes-}, IF_ARCH_sparc(23,
+ IF_ARCH_powerpc( IF_OS_darwin(24,8{-SVR4 ABI: Linux-}), ???))))
\end{code}
% - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
\end{code}
% - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
@@
-116,7
+117,7
@@
save_cands = [BaseReg,Sp,SpLim,Hp,HpLim]
restore_cands = save_cands
volatileSavesOrRestores do_saves vols
restore_cands = save_cands
volatileSavesOrRestores do_saves vols
- = catMaybes (map mkCode vols)
+ = mapCatMaybes mkCode vols
where
mkCode mid
| case mid of { BaseReg -> True; _ -> False }
where
mkCode mid
| case mid of { BaseReg -> True; _ -> False }
@@
-429,7
+430,7
@@
data RI
= RIReg Reg
| RIImm Imm
= RIReg Reg
| RIImm Imm
-#endif {- alpha_TARGET_ARCH -}
+#endif /* alpha_TARGET_ARCH */
\end{code}
Intel, in their infinite wisdom, selected a stack model for floating
\end{code}
Intel, in their infinite wisdom, selected a stack model for floating
@@
-630,7
+631,7
@@
is_G_instr instr
GFREE -> panic "is_G_instr: GFREE (!)"
other -> False
GFREE -> panic "is_G_instr: GFREE (!)"
other -> False
-#endif {- i386_TARGET_ARCH -}
+#endif /* i386_TARGET_ARCH */
\end{code}
\begin{code}
\end{code}
\begin{code}
@@
-715,7
+716,7
@@
moveSp n
fPair :: Reg -> Reg
fPair (RealReg n) | n >= 32 && n `mod` 2 == 0 = RealReg (n+1)
fPair other = pprPanic "fPair(sparc NCG)" (ppr other)
fPair :: Reg -> Reg
fPair (RealReg n) | n >= 32 && n `mod` 2 == 0 = RealReg (n+1)
fPair other = pprPanic "fPair(sparc NCG)" (ppr other)
-#endif {- sparc_TARGET_ARCH -}
+#endif /* sparc_TARGET_ARCH */
\end{code}
\begin{code}
\end{code}
\begin{code}
@@
-736,12
+737,12
@@
fPair other = pprPanic "fPair(sparc NCG)" (ppr other)
| BCC Cond CLabel
| MTCTR Reg
| BCC Cond CLabel
| MTCTR Reg
- | BCTR
+ | BCTR DestInfo
| BL Imm [Reg] -- with list of argument regs
| BCTRL [Reg]
| ADD Reg Reg RI -- dst, src1, src2
| BL Imm [Reg] -- with list of argument regs
| BCTRL [Reg]
| ADD Reg Reg RI -- dst, src1, src2
- | SUBF Reg Reg RI -- dst, src1, src2
+ | SUBF Reg Reg Reg -- dst, src1, src2 ; dst = src2 - src1
| MULLW Reg Reg RI
| DIVW Reg Reg Reg
| DIVWU Reg Reg Reg
| MULLW Reg Reg RI
| DIVW Reg Reg Reg
| DIVWU Reg Reg Reg
@@
-783,6
+784,6
@@
condToSigned LU = LTT
condToSigned GEU = GE
condToSigned LEU = LE
condToSigned x = x
condToSigned GEU = GE
condToSigned LEU = LE
condToSigned x = x
-#endif {- powerpc_TARGET_ARCH -}
+#endif /* powerpc_TARGET_ARCH */
\end{code}
\end{code}