+ adj_code[0x0f] = (unsigned char)0xff; /* jmp *%eax */
+ adj_code[0x10] = (unsigned char)0xe0;
+ }
+#elif defined(sparc_HOST_ARCH)
+ /* Magic constant computed by inspecting the code length of the following
+ assembly language snippet (offset and machine code prefixed):
+
+ <00>: 9C23A008 sub %sp, 8, %sp ! make room for %o4/%o5 in caller's frame
+ <04>: DA23A060 st %o5, [%sp + 96] ! shift registers by 2 positions
+ <08>: D823A05C st %o4, [%sp + 92]
+ <0C>: 9A10000B mov %o3, %o5
+ <10>: 9810000A mov %o2, %o4
+ <14>: 96100009 mov %o1, %o3
+ <18>: 94100008 mov %o0, %o2
+ <1C>: 13000000 sethi %hi(wptr), %o1 ! load up wptr (1 of 2)
+ <20>: 11000000 sethi %hi(hptr), %o0 ! load up hptr (1 of 2)
+ <24>: 81C26000 jmp %o1 + %lo(wptr) ! jump to wptr (load 2 of 2)
+ <28>: 90122000 or %o0, %lo(hptr), %o0 ! load up hptr (2 of 2, delay slot)
+ <2C> 00000000 ! place for getting hptr back easily
+
+ ccall'ing on SPARC is easy, because we are quite lucky to push a
+ multiple of 8 bytes (1 word hptr + 1 word dummy arg) in front of the
+ existing arguments (note that %sp must stay double-word aligned at
+ all times, see ABI spec at http://www.sparc.org/standards/psABI3rd.pdf).
+ To do this, we extend the *caller's* stack frame by 2 words and shift
+ the output registers used for argument passing (%o0 - %o5, we are a *leaf*
+ procedure because of the tail-jump) by 2 positions. This makes room in
+ %o0 and %o1 for the additinal arguments, namely hptr and a dummy (used
+ for destination addr of jump on SPARC, return address on x86, ...). This
+ shouldn't cause any problems for a C-like caller: alloca is implemented
+ similarly, and local variables should be accessed via %fp, not %sp. In a
+ nutshell: This should work! (Famous last words! :-)
+ */
+ adjustor = mallocBytesRWX(4*(11+1));
+ {
+ unsigned long *const adj_code = (unsigned long *)adjustor;
+
+ adj_code[ 0] = 0x9C23A008UL; /* sub %sp, 8, %sp */
+ adj_code[ 1] = 0xDA23A060UL; /* st %o5, [%sp + 96] */
+ adj_code[ 2] = 0xD823A05CUL; /* st %o4, [%sp + 92] */
+ adj_code[ 3] = 0x9A10000BUL; /* mov %o3, %o5 */
+ adj_code[ 4] = 0x9810000AUL; /* mov %o2, %o4 */
+ adj_code[ 5] = 0x96100009UL; /* mov %o1, %o3 */
+ adj_code[ 6] = 0x94100008UL; /* mov %o0, %o2 */
+ adj_code[ 7] = 0x13000000UL; /* sethi %hi(wptr), %o1 */
+ adj_code[ 7] |= ((unsigned long)wptr) >> 10;
+ adj_code[ 8] = 0x11000000UL; /* sethi %hi(hptr), %o0 */
+ adj_code[ 8] |= ((unsigned long)hptr) >> 10;
+ adj_code[ 9] = 0x81C26000UL; /* jmp %o1 + %lo(wptr) */
+ adj_code[ 9] |= ((unsigned long)wptr) & 0x000003FFUL;
+ adj_code[10] = 0x90122000UL; /* or %o0, %lo(hptr), %o0 */
+ adj_code[10] |= ((unsigned long)hptr) & 0x000003FFUL;
+
+ adj_code[11] = (unsigned long)hptr;
+
+ /* flush cache */
+ asm("flush %0" : : "r" (adj_code ));
+ asm("flush %0" : : "r" (adj_code + 2));
+ asm("flush %0" : : "r" (adj_code + 4));
+ asm("flush %0" : : "r" (adj_code + 6));
+ asm("flush %0" : : "r" (adj_code + 10));
+
+ /* max. 5 instructions latency, and we need at >= 1 for returning */
+ asm("nop");
+ asm("nop");
+ asm("nop");
+ asm("nop");
+ }
+#elif defined(alpha_HOST_ARCH)
+ /* Magic constant computed by inspecting the code length of
+ the following assembly language snippet
+ (offset and machine code prefixed; note that the machine code
+ shown is longwords stored in little-endian order):
+
+ <00>: 46520414 mov a2, a4
+ <04>: 46100412 mov a0, a2
+ <08>: a61b0020 ldq a0, 0x20(pv) # load up hptr
+ <0c>: 46730415 mov a3, a5
+ <10>: a77b0028 ldq pv, 0x28(pv) # load up wptr
+ <14>: 46310413 mov a1, a3
+ <18>: 6bfb---- jmp (pv), <hint> # jump to wptr (with hint)
+ <1c>: 00000000 # padding for alignment
+ <20>: [8 bytes for hptr quadword]
+ <28>: [8 bytes for wptr quadword]
+
+ The "computed" jump at <08> above is really a jump to a fixed
+ location. Accordingly, we place an always-correct hint in the
+ jump instruction, namely the address offset from <0c> to wptr,
+ divided by 4, taking the lowest 14 bits.
+
+ We only support passing 4 or fewer argument words, for the same
+ reason described under sparc_HOST_ARCH above by JRS, 21 Aug 01.
+ On the Alpha the first 6 integer arguments are in a0 through a5,
+ and the rest on the stack. Hence we want to shuffle the original
+ caller's arguments by two.
+
+ On the Alpha the calling convention is so complex and dependent
+ on the callee's signature -- for example, the stack pointer has
+ to be a multiple of 16 -- that it seems impossible to me [ccshan]
+ to handle the general case correctly without changing how the
+ adjustor is called from C. For now, our solution of shuffling
+ registers only and ignoring the stack only works if the original
+ caller passed 4 or fewer argument words.
+
+TODO: Depending on how much allocation overhead stgMallocBytes uses for
+ header information (more precisely, if the overhead is no more than
+ 4 bytes), we should move the first three instructions above down by
+ 4 bytes (getting rid of the nop), hence saving memory. [ccshan]
+ */
+ ASSERT(((StgWord64)wptr & 3) == 0);
+ adjustor = mallocBytesRWX(48);
+ {
+ StgWord64 *const code = (StgWord64 *)adjustor;
+
+ code[0] = 0x4610041246520414L;
+ code[1] = 0x46730415a61b0020L;
+ code[2] = 0x46310413a77b0028L;
+ code[3] = 0x000000006bfb0000L
+ | (((StgWord32*)(wptr) - (StgWord32*)(code) - 3) & 0x3fff);
+
+ code[4] = (StgWord64)hptr;
+ code[5] = (StgWord64)wptr;
+
+ /* Ensure that instruction cache is consistent with our new code */
+ __asm__ volatile("call_pal %0" : : "i" (PAL_imb));
+ }
+#elif defined(powerpc_HOST_ARCH) && defined(linux_HOST_OS)
+
+#define OP_LO(op,lo) ((((unsigned)(op)) << 16) | (((unsigned)(lo)) & 0xFFFF))
+#define OP_HI(op,hi) ((((unsigned)(op)) << 16) | (((unsigned)(hi)) >> 16))
+ {
+ /* The PowerPC Linux (32-bit) calling convention is annoyingly complex.
+ We need to calculate all the details of the stack frame layout,
+ taking into account the types of all the arguments, and then
+ generate code on the fly. */
+
+ int src_gpr = 3, dst_gpr = 5;
+ int fpr = 3;
+ int src_offset = 0, dst_offset = 0;
+ int n = strlen(typeString),i;
+ int src_locs[n], dst_locs[n];
+ int frameSize;
+ unsigned *code;
+
+ /* Step 1:
+ Calculate where the arguments should go.
+ src_locs[] will contain the locations of the arguments in the
+ original stack frame passed to the adjustor.
+ dst_locs[] will contain the locations of the arguments after the
+ adjustor runs, on entry to the wrapper proc pointed to by wptr.
+
+ This algorithm is based on the one described on page 3-19 of the
+ System V ABI PowerPC Processor Supplement.
+ */
+ for(i=0;typeString[i];i++)
+ {
+ char t = typeString[i];
+ if((t == 'f' || t == 'd') && fpr <= 8)
+ src_locs[i] = dst_locs[i] = -32-(fpr++);
+ else
+ {
+ if(t == 'l' && src_gpr <= 9)
+ {
+ if((src_gpr & 1) == 0)
+ src_gpr++;
+ src_locs[i] = -src_gpr;
+ src_gpr += 2;
+ }
+ else if(t == 'i' && src_gpr <= 10)
+ {
+ src_locs[i] = -(src_gpr++);
+ }
+ else
+ {
+ if(t == 'l' || t == 'd')
+ {
+ if(src_offset % 8)
+ src_offset += 4;
+ }
+ src_locs[i] = src_offset;
+ src_offset += (t == 'l' || t == 'd') ? 8 : 4;
+ }
+
+ if(t == 'l' && dst_gpr <= 9)
+ {
+ if((dst_gpr & 1) == 0)
+ dst_gpr++;
+ dst_locs[i] = -dst_gpr;
+ dst_gpr += 2;
+ }
+ else if(t == 'i' && dst_gpr <= 10)
+ {
+ dst_locs[i] = -(dst_gpr++);
+ }
+ else
+ {
+ if(t == 'l' || t == 'd')
+ {
+ if(dst_offset % 8)
+ dst_offset += 4;
+ }
+ dst_locs[i] = dst_offset;
+ dst_offset += (t == 'l' || t == 'd') ? 8 : 4;
+ }
+ }
+ }
+
+ frameSize = dst_offset + 8;
+ frameSize = (frameSize+15) & ~0xF;
+
+ /* Step 2:
+ Build the adjustor.
+ */
+ // allocate space for at most 4 insns per parameter
+ // plus 14 more instructions.
+ adjustor = mallocBytesRWX(4 * (4*n + 14));
+ code = (unsigned*)adjustor;
+
+ *code++ = 0x48000008; // b *+8
+ // * Put the hptr in a place where freeHaskellFunctionPtr
+ // can get at it.
+ *code++ = (unsigned) hptr;
+
+ // * save the link register
+ *code++ = 0x7c0802a6; // mflr r0;
+ *code++ = 0x90010004; // stw r0, 4(r1);
+ // * and build a new stack frame
+ *code++ = OP_LO(0x9421, -frameSize); // stwu r1, -frameSize(r1)
+
+ // * now generate instructions to copy arguments
+ // from the old stack frame into the new stack frame.
+ for(i=n-1;i>=0;i--)
+ {
+ if(src_locs[i] < -32)
+ ASSERT(dst_locs[i] == src_locs[i]);
+ else if(src_locs[i] < 0)
+ {
+ // source in GPR.
+ ASSERT(typeString[i] != 'f' && typeString[i] != 'd');
+ if(dst_locs[i] < 0)
+ {
+ ASSERT(dst_locs[i] > -32);
+ // dst is in GPR, too.
+
+ if(typeString[i] == 'l')
+ {
+ // mr dst+1, src+1
+ *code++ = 0x7c000378
+ | ((-dst_locs[i]+1) << 16)
+ | ((-src_locs[i]+1) << 11)
+ | ((-src_locs[i]+1) << 21);
+ }
+ // mr dst, src
+ *code++ = 0x7c000378
+ | ((-dst_locs[i]) << 16)
+ | ((-src_locs[i]) << 11)
+ | ((-src_locs[i]) << 21);
+ }
+ else
+ {
+ if(typeString[i] == 'l')
+ {
+ // stw src+1, dst_offset+4(r1)
+ *code++ = 0x90010000
+ | ((-src_locs[i]+1) << 21)
+ | (dst_locs[i] + 4);
+ }
+
+ // stw src, dst_offset(r1)
+ *code++ = 0x90010000
+ | ((-src_locs[i]) << 21)
+ | (dst_locs[i] + 8);
+ }
+ }
+ else
+ {
+ ASSERT(dst_locs[i] >= 0);
+ ASSERT(typeString[i] != 'f' && typeString[i] != 'd');
+
+ if(typeString[i] == 'l')
+ {
+ // lwz r0, src_offset(r1)
+ *code++ = 0x80010000
+ | (src_locs[i] + frameSize + 8 + 4);
+ // stw r0, dst_offset(r1)
+ *code++ = 0x90010000
+ | (dst_locs[i] + 8 + 4);
+ }
+ // lwz r0, src_offset(r1)
+ *code++ = 0x80010000
+ | (src_locs[i] + frameSize + 8);
+ // stw r0, dst_offset(r1)
+ *code++ = 0x90010000
+ | (dst_locs[i] + 8);
+ }
+ }
+
+ // * hptr will be the new first argument.
+ // lis r3, hi(hptr)
+ *code++ = OP_HI(0x3c60, hptr);
+ // ori r3,r3,lo(hptr)
+ *code++ = OP_LO(0x6063, hptr);
+
+ // * we need to return to a piece of code
+ // which will tear down the stack frame.
+ // lis r11,hi(obscure_ccall_ret_code)
+ *code++ = OP_HI(0x3d60, obscure_ccall_ret_code);
+ // ori r11,r11,lo(obscure_ccall_ret_code)
+ *code++ = OP_LO(0x616b, obscure_ccall_ret_code);
+ // mtlr r11
+ *code++ = 0x7d6803a6;
+
+ // * jump to wptr
+ // lis r11,hi(wptr)
+ *code++ = OP_HI(0x3d60, wptr);
+ // ori r11,r11,lo(wptr)
+ *code++ = OP_LO(0x616b, wptr);
+ // mtctr r11
+ *code++ = 0x7d6903a6;
+ // bctr
+ *code++ = 0x4e800420;
+
+ // Flush the Instruction cache:
+ {
+ unsigned *p = adjustor;
+ while(p < code)
+ {
+ __asm__ volatile ("dcbf 0,%0\n\tsync\n\ticbi 0,%0"
+ : : "r" (p));
+ p++;
+ }
+ __asm__ volatile ("sync\n\tisync");
+ }
+ }