+ register long real_ra __asm__("$26"); volatile long save_ra;
+ register long real_gp __asm__("$29"); volatile long save_gp;
+
+ register long real_s0 __asm__("$9" ); volatile long save_s0;
+ register long real_s1 __asm__("$10"); volatile long save_s1;
+ register long real_s2 __asm__("$11"); volatile long save_s2;
+ register long real_s3 __asm__("$12"); volatile long save_s3;
+ register long real_s4 __asm__("$13"); volatile long save_s4;
+ register long real_s5 __asm__("$14"); volatile long save_s5;
+#ifdef alpha_EXTRA_CAREFUL
+ register long real_s6 __asm__("$15"); volatile long save_s6;
+#endif
+
+ register double real_f2 __asm__("$f2"); volatile double save_f2;
+ register double real_f3 __asm__("$f3"); volatile double save_f3;
+ register double real_f4 __asm__("$f4"); volatile double save_f4;
+ register double real_f5 __asm__("$f5"); volatile double save_f5;
+ register double real_f6 __asm__("$f6"); volatile double save_f6;
+ register double real_f7 __asm__("$f7"); volatile double save_f7;
+#ifdef alpha_EXTRA_CAREFUL
+ register double real_f8 __asm__("$f8"); volatile double save_f8;
+ register double real_f9 __asm__("$f9"); volatile double save_f9;
+#endif
+
+ register StgFunPtr real_pv __asm__("$27");
+
+ StgThreadReturnCode ret;
+
+ save_ra = real_ra;
+ save_gp = real_gp;
+
+ save_s0 = real_s0;
+ save_s1 = real_s1;
+ save_s2 = real_s2;
+ save_s3 = real_s3;
+ save_s4 = real_s4;
+ save_s5 = real_s5;
+#ifdef alpha_EXTRA_CAREFUL
+ save_s6 = real_s6;
+#endif
+
+ save_f2 = real_f2;
+ save_f3 = real_f3;
+ save_f4 = real_f4;
+ save_f5 = real_f5;
+ save_f6 = real_f6;
+ save_f7 = real_f7;
+#ifdef alpha_EXTRA_CAREFUL
+ save_f8 = real_f8;
+ save_f9 = real_f9;
+#endif
+
+ real_pv = f;
+
+ __asm__ volatile( "lda $30,-%0($30)" "\n"
+ "\t" "jmp ($27)" "\n"
+ "\t" ".align 3" "\n"
+ ".globl " STG_RETURN "\n"
+ STG_RETURN ":" "\n"
+ "\t" "lda $30,%0($30)" "\n"
+ : : "K" (RESERVED_C_STACK_BYTES));
+
+ ret = real_s5;
+
+ real_s0 = save_s0;
+ real_s1 = save_s1;
+ real_s2 = save_s2;
+ real_s3 = save_s3;
+ real_s4 = save_s4;
+ real_s5 = save_s5;
+#ifdef alpha_EXTRA_CAREFUL
+ real_s6 = save_s6;
+#endif
+
+ real_f2 = save_f2;
+ real_f3 = save_f3;
+ real_f4 = save_f4;
+ real_f5 = save_f5;
+ real_f6 = save_f6;
+ real_f7 = save_f7;
+#ifdef alpha_EXTRA_CAREFUL
+ real_f8 = save_f8;
+ real_f9 = save_f9;
+#endif
+
+ real_ra = save_ra;
+ real_gp = save_gp;
+
+ return ret;
+}
+
+#endif /* alpha_TARGET_ARCH */
+
+/* -----------------------------------------------------------------------------
+ HP-PA architecture
+ -------------------------------------------------------------------------- */
+
+#ifdef hppa1_1_TARGET_ARCH
+
+StgThreadReturnCode
+StgRun(StgFunPtr f, StgRegTable *basereg)
+{
+ StgChar space[RESERVED_C_STACK_BYTES+16*sizeof(long)+10*sizeof(double)];
+ StgThreadReturnCode ret;
+
+ __asm__ volatile ("ldo %0(%%r30),%%r19\n"
+ "\tstw %%r3, 0(0,%%r19)\n"
+ "\tstw %%r4, 4(0,%%r19)\n"
+ "\tstw %%r5, 8(0,%%r19)\n"
+ "\tstw %%r6,12(0,%%r19)\n"
+ "\tstw %%r7,16(0,%%r19)\n"
+ "\tstw %%r8,20(0,%%r19)\n"
+ "\tstw %%r9,24(0,%%r19)\n"
+ "\tstw %%r10,28(0,%%r19)\n"
+ "\tstw %%r11,32(0,%%r19)\n"
+ "\tstw %%r12,36(0,%%r19)\n"
+ "\tstw %%r13,40(0,%%r19)\n"
+ "\tstw %%r14,44(0,%%r19)\n"
+ "\tstw %%r15,48(0,%%r19)\n"
+ "\tstw %%r16,52(0,%%r19)\n"
+ "\tstw %%r17,56(0,%%r19)\n"
+ "\tstw %%r18,60(0,%%r19)\n"
+ "\tldo 80(%%r19),%%r19\n"
+ "\tfstds %%fr12,-16(0,%%r19)\n"
+ "\tfstds %%fr13, -8(0,%%r19)\n"
+ "\tfstds %%fr14, 0(0,%%r19)\n"
+ "\tfstds %%fr15, 8(0,%%r19)\n"
+ "\tldo 32(%%r19),%%r19\n"
+ "\tfstds %%fr16,-16(0,%%r19)\n"
+ "\tfstds %%fr17, -8(0,%%r19)\n"
+ "\tfstds %%fr18, 0(0,%%r19)\n"
+ "\tfstds %%fr19, 8(0,%%r19)\n"
+ "\tldo 32(%%r19),%%r19\n"
+ "\tfstds %%fr20,-16(0,%%r19)\n"
+ "\tfstds %%fr21, -8(0,%%r19)\n" : :
+ "n" (-(116 * sizeof(long) + 10 * sizeof(double))) : "%r19"
+ );