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one more bugfix: a load/load memory barrier is required in stealWSDeque_()
[ghc-hetmet.git]
/
rts
/
parallel
/
WSDeque.c
diff --git
a/rts/parallel/WSDeque.c
b/rts/parallel/WSDeque.c
index
4ae9417
..
f77ff09
100644
(file)
--- a/
rts/parallel/WSDeque.c
+++ b/
rts/parallel/WSDeque.c
@@
-186,8
+186,11
@@
stealWSDeque_ (WSDeque *q)
// Can't do this on someone else's spark pool:
// ASSERT_WSDEQUE_INVARIANTS(q);
// Can't do this on someone else's spark pool:
// ASSERT_WSDEQUE_INVARIANTS(q);
- b = q->bottom;
+ // NB. these loads must be ordered, otherwise there is a race
+ // between steal and pop.
t = q->top;
t = q->top;
+ load_load_barrier();
+ b = q->bottom;
// NB. b and t are unsigned; we need a signed value for the test
// below, because it is possible that t > b during a
// NB. b and t are unsigned; we need a signed value for the test
// below, because it is possible that t > b during a