-- * Machine instructions
Instr(..),
Cond(..), condUnsigned, condToSigned, condToUnsigned,
-
+#if powerpc_TARGET_ARCH
+ condNegate,
+#endif
#if !powerpc_TARGET_ARCH && !i386_TARGET_ARCH && !x86_64_TARGET_ARCH
Size(..), machRepSize,
#endif
-- Our flavours of the Cmm types
-- Type synonyms for Cmm populated with native code
-type NatCmm = GenCmm CmmStatic Instr
-type NatCmmTop = GenCmmTop CmmStatic Instr
+type NatCmm = GenCmm CmmStatic [CmmStatic] Instr
+type NatCmmTop = GenCmmTop CmmStatic [CmmStatic] Instr
type NatBasicBlock = GenBasicBlock Instr
-- -----------------------------------------------------------------------------
condToUnsigned LE = LEU
condToUnsigned x = x
+#if powerpc_TARGET_ARCH
+condNegate ALWAYS = panic "condNegate: ALWAYS"
+condNegate EQQ = NE
+condNegate GE = LTT
+condNegate GEU = LU
+condNegate GTT = LE
+condNegate GU = LEU
+condNegate LE = GTT
+condNegate LEU = GU
+condNegate LTT = GE
+condNegate LU = GEU
+condNegate NE = EQQ
+#endif
+
-- -----------------------------------------------------------------------------
-- Sizes on this architecture
| CVTSS2SD Reg Reg -- F32 to F64
| CVTSD2SS Reg Reg -- F64 to F32
- | CVTSS2SI Operand Reg -- F32 to I32/I64 (with rounding)
- | CVTSD2SI Operand Reg -- F64 to I32/I64 (with rounding)
+ | CVTTSS2SIQ Operand Reg -- F32 to I32/I64 (with truncation)
+ | CVTTSD2SIQ Operand Reg -- F64 to I32/I64 (with truncation)
| CVTSI2SS Operand Reg -- I32/I64 to F32
| CVTSI2SD Operand Reg -- I32/I64 to F64
-- Jumping around.
| JMP Operand
| JXX Cond BlockId -- includes unconditional branches
+ | JXX_GBL Cond Imm -- non-local version of JXX
| JMP_TBL Operand [BlockId] -- table jump
| CALL (Either Imm Reg) [Reg]
| CMPL MachRep Reg RI --- size, src1, src2
| BCC Cond BlockId
+ | BCCFAR Cond BlockId
| JMP CLabel -- same as branch,
-- but with CLabel instead of block ID
| MTCTR Reg
| FETCHPC Reg -- pseudo-instruction:
-- bcl to next insn, mflr reg
+ | LWSYNC -- memory barrier
#endif /* powerpc_TARGET_ARCH */