SPARC NCG: Add support for hardware divide

[ghc-hetmet.git] / compiler / nativeGen / PprMach.hs

diff --git a/compiler/nativeGen/PprMach.hs b/compiler/nativeGen/PprMach.hs
index 822dc0d..199fd36 100644 (file)
--- a/compiler/nativeGen/PprMach.hs
+++ b/compiler/nativeGen/PprMach.hs
@@ -395,8 +395,8 @@ pprSize x = ptext (case x of
        FF64  -> sLit "sd"      -- "scalar double-precision float" (SSE2)
 #endif
 #if sparc_TARGET_ARCH
-       II8   -> sLit "sb"
-        II16  -> sLit "sh"
+       II8   -> sLit "ub"
+        II16  -> sLit "uh"
        II32  -> sLit ""
        II64  -> sLit "d"
        FF32  -> sLit ""
@@ -2002,9 +2002,19 @@ pprInstr (SLL reg1 ri reg2) = pprRegRIReg (sLit "sll") False reg1 ri reg2
 pprInstr (SRL reg1 ri reg2) = pprRegRIReg (sLit "srl") False reg1 ri reg2
 pprInstr (SRA reg1 ri reg2) = pprRegRIReg (sLit "sra") False reg1 ri reg2
 
-pprInstr (RDY rd) = ptext (sLit "\trd\t%y,") <> pprReg rd
-pprInstr (SMUL b reg1 ri reg2) = pprRegRIReg (sLit "smul")  b reg1 ri reg2
-pprInstr (UMUL b reg1 ri reg2) = pprRegRIReg (sLit "umul")  b reg1 ri reg2
+pprInstr (RDY rd)              = ptext (sLit "\trd\t%y,") <> pprReg rd
+pprInstr (WRY reg1 reg2)       
+       = ptext (sLit "\twr\t") 
+               <> pprReg reg1 
+               <> char ','
+               <> pprReg reg2
+               <> char ','
+               <> ptext (sLit "%y") 
+
+pprInstr (SMUL b reg1 ri reg2) = pprRegRIReg (sLit "smul")  b reg1 ri reg2
+pprInstr (UMUL b reg1 ri reg2) = pprRegRIReg (sLit "umul")  b reg1 ri reg2
+pprInstr (SDIV b reg1 ri reg2) = pprRegRIReg (sLit "sdiv")  b reg1 ri reg2
+pprInstr (UDIV b reg1 ri reg2) = pprRegRIReg (sLit "udiv")  b reg1 ri reg2
 
 pprInstr (SETHI imm reg)
   = hcat [