[project @ 2000-08-07 23:37:19 by qrczak]

[ghc-hetmet.git] / ghc / compiler / codeGen / CgRetConv.lhs

diff --git a/ghc/compiler/codeGen/CgRetConv.lhs b/ghc/compiler/codeGen/CgRetConv.lhs
index 9dc622a..4c0151e 100644 (file)
--- a/ghc/compiler/codeGen/CgRetConv.lhs
+++ b/ghc/compiler/codeGen/CgRetConv.lhs
@@ -1,7 +1,7 @@
 %
 % (c) The GRASP Project, Glasgow University, 1992-1998
 %
-% $Id: CgRetConv.lhs,v 1.17 1999/01/18 14:31:51 sof Exp $
+% $Id: CgRetConv.lhs,v 1.24 2000/08/07 23:37:20 qrczak Exp $
 %
 \section[CgRetConv]{Return conventions for the code generator}
 
@@ -21,17 +21,14 @@ module CgRetConv (
 import AbsCSyn         -- quite a few things
 import Constants       ( mAX_FAMILY_SIZE_FOR_VEC_RETURNS,
                          mAX_Vanilla_REG, mAX_Float_REG,
-                         mAX_Double_REG, mAX_Real_Double_REG,
-                         mAX_Real_Vanilla_REG, mAX_Real_Float_REG,
-                         mAX_Long_REG, mAX_Real_Long_REG
+                         mAX_Double_REG, mAX_Long_REG
+                       )
+import CmdLineOpts     ( opt_UseVanillaRegs, opt_UseFloatRegs,
+                         opt_UseDoubleRegs, opt_UseLongRegs
                        )
 import Maybes          ( catMaybes )
-import DataCon         ( dataConRawArgTys, DataCon )
-import PrimOp          ( PrimOp{-instance Outputable-} )
 import PrimRep         ( isFloatingRep, PrimRep(..), is64BitRep )
-import TyCon           ( TyCon, tyConDataCons, tyConFamilySize )
-import Type            ( Type, typePrimRep, isUnLiftedType, 
-                         splitAlgTyConApp_maybe )
+import TyCon           ( TyCon, tyConFamilySize )
 import Util            ( isn'tIn )
 
 import Outputable
@@ -84,6 +81,7 @@ dataReturnConvPrim Int64Rep   = LongReg Int64Rep  ILIT(1)
 dataReturnConvPrim Word64Rep   = LongReg Word64Rep ILIT(1)
 dataReturnConvPrim AddrRep     = VanillaReg AddrRep ILIT(1)
 dataReturnConvPrim CharRep     = VanillaReg CharRep ILIT(1)
+dataReturnConvPrim Int8Rep     = VanillaReg Int8Rep ILIT(1)
 dataReturnConvPrim FloatRep    = FloatReg  ILIT(1)
 dataReturnConvPrim DoubleRep   = DoubleReg ILIT(1)
 dataReturnConvPrim VoidRep     = VoidReg
@@ -182,16 +180,19 @@ that are guaranteed to map to machine registers.
 
 \begin{code}
 vanillaRegNos, floatRegNos, doubleRegNos, longRegNos :: [Int]
-vanillaRegNos   = [1 .. mAX_Real_Vanilla_REG]
-floatRegNos     = [1 .. mAX_Real_Float_REG]
-doubleRegNos    = [1 .. mAX_Real_Double_REG]
-longRegNos       = [1 .. mAX_Real_Long_REG]
+vanillaRegNos   = regList opt_UseVanillaRegs
+floatRegNos     = regList opt_UseFloatRegs
+doubleRegNos    = regList opt_UseDoubleRegs
+longRegNos       = regList opt_UseLongRegs
 
 allVanillaRegNos, allFloatRegNos, allDoubleRegNos, allLongRegNos :: [Int]
-allVanillaRegNos = [1 .. mAX_Vanilla_REG]
-allFloatRegNos  = [1 .. mAX_Float_REG]
-allDoubleRegNos         = [1 .. mAX_Double_REG]
-allLongRegNos   = [1 .. mAX_Long_REG]
+allVanillaRegNos = regList mAX_Vanilla_REG
+allFloatRegNos  = regList mAX_Float_REG
+allDoubleRegNos         = regList mAX_Double_REG
+allLongRegNos   = regList mAX_Long_REG
+
+regList 0 = []
+regList n = [1 .. n]
 
 type AvailRegs = ( [Int]   -- available vanilla regs.
                 , [Int]   -- floats