import Outputable
import SrcLoc ( SrcLoc )
import Bag
-import Module ( ModuleName, pprModuleName )
+import Module ( ModuleName )
\end{code}
All we actually declare here is the top-level structure for a module.
Nothing -> pp_modname <+> rest
Just d -> vcat [ pp_modname, ppr d, rest ]
- pp_modname = ptext SLIT("module") <+> pprModuleName name
+ pp_modname = ptext SLIT("module") <+> ppr name
pp_nonnull [] = empty
pp_nonnull xs = vcat (map ppr xs)