import MachRegs
import RegAllocInfo
-import FiniteMap ( FiniteMap, emptyFM, addListToFM, delListFromFM,
- lookupFM, keysFM, eltsFM, mapFM, addToFM_C, addToFM,
- listToFM, fmToList, lookupWithDefaultFM )
-import Unique ( mkBuiltinUnique )
-import OrdList ( unitOL, appOL, fromOL, concatOL )
+import FiniteMap ( FiniteMap, emptyFM,
+ lookupFM, eltsFM, addToFM_C, addToFM,
+ listToFM, fmToList )
+import OrdList ( fromOL )
import Outputable
-import Unique ( Unique, Uniquable(..), mkPseudoUnique3 )
+import Unique ( mkPseudoUnique3 )
import CLabel ( CLabel, pprCLabel )
import FastTypes
$$
(text "code = ")
$$
- (vcat (map pprInstr flatInstrs))
+ (vcat (map (docToSDoc.pprInstr) flatInstrs))
)
tryGeneral (resv:resvs)
= case generalAlloc resv of
insertSpillCode :: [Instr] -> [Instr]
insertSpillCode insns
= let uniques_in_insns
- = map getUnique
+ = map getVRegUnique
(regSetToList
(foldl unionRegSets emptyRegSet
(map vregs_in_insn insns)))
= case regUsage i of
RU rds wrs -> filterRegSet isVirtualReg
(rds `unionRegSets` wrs)
- vreg_to_slot_map :: FiniteMap Unique Int
+ vreg_to_slot_map :: FiniteMap VRegUnique Int
vreg_to_slot_map
= listToFM (zip uniques_in_insns [0..])
-- to the stack pointer, as opposed to the frame pointer. The other is a
-- counter, used to manufacture new temporary register names.
-patchInstr :: FiniteMap Unique Int -> (Int,Int) -> Instr -> ((Int,Int), [Instr])
+patchInstr :: FiniteMap VRegUnique Int -> (Int,Int) -> Instr -> ((Int,Int), [Instr])
patchInstr vreg_to_slot_map (delta,ctr) instr
| null memSrcs && null memDsts
| isVirtualReg vreg
= case [vi | (vreg', vi) <- vreg_env, vreg' == vreg] of
[i] -> case regClass vreg of
- RcInteger -> VirtualRegI (mkPseudoUnique3 i)
- RcFloat -> VirtualRegF (mkPseudoUnique3 i)
- RcDouble -> VirtualRegD (mkPseudoUnique3 i)
+ RcInteger -> VirtualRegI (pseudoVReg i)
+ RcFloat -> VirtualRegF (pseudoVReg i)
+ RcDouble -> VirtualRegD (pseudoVReg i)
_ -> pprPanic "patchInstr: unmapped VReg" (ppr vreg)
| otherwise
= vreg
+ pseudoVReg i = VRegUniqueLo (mkPseudoUnique3 i)
+
memSrcs = filter isVirtualReg (regSetToList srcs)
memDsts = filter isVirtualReg (regSetToList dsts)