[project @ 2000-02-28 12:02:31 by sewardj]

[ghc-hetmet.git] / ghc / compiler / nativeGen / MachMisc.lhs

diff --git a/ghc/compiler/nativeGen/MachMisc.lhs b/ghc/compiler/nativeGen/MachMisc.lhs
index 867495b..ddbc1fd 100644 (file)
--- a/ghc/compiler/nativeGen/MachMisc.lhs
+++ b/ghc/compiler/nativeGen/MachMisc.lhs
@@ -301,6 +301,7 @@ data Size
     | L
     | F            -- IEEE single-precision floating pt
     | DF    -- IEEE single-precision floating pt
+    | F80   -- Intel 80-bit internal FP format; only used for spilling
 #endif
 #if sparc_TARGET_ARCH
     = B     -- byte (signed)
@@ -320,7 +321,7 @@ primRepToSize CodePtrRep    = IF_ARCH_alpha( Q,      IF_ARCH_i386( L, IF_ARCH_sparc(
 primRepToSize DataPtrRep    = IF_ARCH_alpha( Q,         IF_ARCH_i386( L, IF_ARCH_sparc( W ,)))
 primRepToSize RetRep       = IF_ARCH_alpha( Q,  IF_ARCH_i386( L, IF_ARCH_sparc( W ,)))
 primRepToSize CostCentreRep = IF_ARCH_alpha( Q,         IF_ARCH_i386( L, IF_ARCH_sparc( W ,)))
-primRepToSize CharRep      = IF_ARCH_alpha( BU, IF_ARCH_i386( L, IF_ARCH_sparc( BU,)))
+primRepToSize CharRep      = IF_ARCH_alpha( BU, IF_ARCH_i386( B, IF_ARCH_sparc( BU,)))
 primRepToSize IntRep       = IF_ARCH_alpha( Q,  IF_ARCH_i386( L, IF_ARCH_sparc( W ,)))
 primRepToSize WordRep      = IF_ARCH_alpha( Q,  IF_ARCH_i386( L, IF_ARCH_sparc( W ,)))
 primRepToSize AddrRep      = IF_ARCH_alpha( Q,  IF_ARCH_i386( L, IF_ARCH_sparc( W ,)))
@@ -351,6 +352,8 @@ data Instr
            String              -- the literal string
   | DATA    Size
            [Imm]
+  | DELTA   Int                 -- specify current stack offset for
+                                -- benefit of subsequent passes
 \end{code}
 
 \begin{code}
@@ -470,6 +473,10 @@ contents, would not impose a fixed mapping from %fake to %st regs, and
 hopefully could avoid most of the redundant reg-reg moves of the
 current translation.
 
+We might as well make use of whatever unique FP facilities Intel have
+chosen to bless us with (let's not be churlish, after all).
+Hence GLDZ and GLD1.  Bwahahahahahahaha!
+
 \begin{code}
 #if i386_TARGET_ARCH
 
@@ -478,8 +485,8 @@ current translation.
 -- Moves.
 
              | MOV           Size Operand Operand
-             | MOVZX         Size Operand Operand -- size is the size of operand 2
-             | MOVSX         Size Operand Operand -- size is the size of operand 2
+             | MOVZxL        Size Operand Operand -- size is the size of operand 1
+             | MOVSxL        Size Operand Operand -- size is the size of operand 1
 
 -- Load effective address (also a very useful three-operand add instruction :-)
 
@@ -503,15 +510,16 @@ current translation.
              | XOR           Size Operand Operand
              | NOT           Size Operand
              | NEGI          Size Operand -- NEG instruction (name clash with Cond)
-             | SHL           Size Operand Operand -- 1st operand must be an Imm or CL
-             | SAR           Size Operand Operand -- 1st operand must be an Imm or CL
-             | SHR           Size Operand Operand -- 1st operand must be an Imm or CL
+             | SHL           Size Imm Operand -- Only immediate shifts allowed
+             | SAR           Size Imm Operand -- Only immediate shifts allowed
+             | SHR           Size Imm Operand -- Only immediate shifts allowed
+              | BT            Size Imm Operand
              | NOP
 
--- Float Arithmetic. -- ToDo for 386
+-- Float Arithmetic.
 
--- Note that we cheat by treating G{ABS,MOV,NEG} of doubles as single instructions
--- right up until we spit them out.
+-- Note that we cheat by treating G{ABS,MOV,NEG} of doubles 
+-- as single instructions right up until we spit them out.
 
               -- all the 3-operand fake fp insns are src1 src2 dst
               -- and furthermore are constrained to be fp regs only.
@@ -520,6 +528,9 @@ current translation.
               | GLD           Size MachRegsAddr Reg -- src, dst(fpreg)
               | GST           Size Reg MachRegsAddr -- src(fpreg), dst
 
+              | GLDZ          Reg -- dst(fpreg)
+              | GLD1          Reg -- dst(fpreg)
+
              | GFTOD         Reg Reg -- src(fpreg), dst(fpreg)
               | GFTOI         Reg Reg -- src(fpreg), dst(intreg)
 
@@ -539,6 +550,9 @@ current translation.
              | GABS          Size Reg Reg -- src, dst
              | GNEG          Size Reg Reg -- src, dst
              | GSQRT         Size Reg Reg -- src, dst
+             | GSIN          Size Reg Reg -- src, dst
+             | GCOS          Size Reg Reg -- src, dst
+             | GTAN          Size Reg Reg -- src, dst
 
               | GFREE         -- do ffree on all x86 regs; an ugly hack
 -- Comparison
@@ -591,6 +605,7 @@ is_G_instr :: Instr -> Bool
 is_G_instr instr
    = case instr of
         GMOV _ _ -> True; GLD _ _ _ -> True; GST _ _ _ -> True;
+        GLDZ _ -> True; GLD1 _ -> True;
         GFTOD _ _ -> True; GFTOI _ _ -> True;
         GDTOF _ _ -> True; GDTOI _ _ -> True;
         GITOF _ _ -> True; GITOD _ _ -> True;
@@ -598,6 +613,7 @@ is_G_instr instr
        GSUB _ _ _ _ -> True; GMUL _ _ _ _ -> True
        GCMP _ _ _ -> True; GABS _ _ _ -> True
        GNEG _ _ _ -> True; GSQRT _ _ _ -> True
+        GSIN _ _ _ -> True; GCOS _ _ _ -> True; GTAN _ _ _ -> True;
         GFREE -> panic "is_G_instr: GFREE (!)"
         other -> False