[project @ 2002-01-02 12:27:43 by simonmar]

[ghc-hetmet.git] / ghc / compiler / nativeGen / MachMisc.lhs

diff --git a/ghc/compiler/nativeGen/MachMisc.lhs b/ghc/compiler/nativeGen/MachMisc.lhs
index 4229595..de69ab6 100644 (file)
--- a/ghc/compiler/nativeGen/MachMisc.lhs
+++ b/ghc/compiler/nativeGen/MachMisc.lhs
@@ -231,6 +231,7 @@ data Cond
   | VC
   | VS
 #endif
+    deriving Eq  -- to make an assertion work
 \end{code}
 
 \begin{code}
@@ -487,6 +488,8 @@ but we don't care, since it doesn't get used much.  We hope.
              | SUB           Size Operand Operand
              | IMUL          Size Operand Operand      -- signed int mul
              | MUL           Size Operand Operand      -- unsigned int mul
+              | IMUL64       Reg Reg                   -- 32 x 32 -> 64 signed mul
+               -- operand1:operand2 := (operand1[31:0] *signed operand2[31:0])
 
 -- Quotient and remainder.  SEE comment above -- these are not
 -- real x86 insns; instead they are expanded when printed
@@ -536,7 +539,11 @@ but we don't care, since it doesn't get used much.  We hope.
              | GSUB          Size Reg Reg Reg -- src1, src2, dst
              | GMUL          Size Reg Reg Reg -- src1, src2, dst
 
-             | GCMP          Size Reg Reg -- src1, src2
+               -- FP compare.  Cond must be `elem` [EQQ, NE, LE, LTT, GE, GTT]
+               -- Compare src1 with src2; set the Zero flag iff the numbers are
+               -- comparable and the comparison is True.  Subsequent code must
+               -- test the %eflags zero flag regardless of the supplied Cond.
+             | GCMP          Cond Reg Reg -- src1, src2
 
              | GABS          Size Reg Reg -- src, dst
              | GNEG          Size Reg Reg -- src, dst
@@ -628,6 +635,9 @@ is_G_instr instr
 
              | ADD           Bool Bool Reg RI Reg -- x?, cc?, src1, src2, dst
              | SUB           Bool Bool Reg RI Reg -- x?, cc?, src1, src2, dst
+             | UMUL               Bool Reg RI Reg --     cc?, src1, src2, dst
+             | SMUL               Bool Reg RI Reg --     cc?, src1, src2, dst
+              | RDY           Reg      -- move contents of Y register to reg
 
 -- Simple bit-twiddling.