callClobberedRegs,
callerSaves,
extractMappedRegNos,
+ mappedRegNo,
freeMappedRegs,
freeReg, freeRegs,
getNewRegNCG,
magicIdRegMaybe,
mkReg,
realReg,
- reservedRegs,
saveLoc,
spRel,
stgReg,
#endif
#if i386_TARGET_ARCH
, eax, ebx, ecx, edx, esi, esp
- , st0, st1, st2, st3, st4, st5, st6, st7
+ , fake0, fake1, fake2, fake3, fake4, fake5
#endif
#if sparc_TARGET_ARCH
, allArgRegs
import CLabel ( CLabel )
import PrimOp ( PrimOp(..) )
import PrimRep ( PrimRep(..) )
-import Stix ( sStLitLbl, StixTree(..), StixReg(..) )
+import Stix ( sStLitLbl, StixTree(..), StixReg(..),
+ getUniqueNat, returnNat, thenNat, NatM )
import Unique ( mkPseudoUnique1, mkPseudoUnique2, mkPseudoUnique3,
Uniquable(..), Unique
)
-import UniqSupply ( getUniqueUs, returnUs, thenUs, UniqSM )
+--import UniqSupply ( getUniqueUs, returnUs, thenUs, UniqSM )
import Outputable
\end{code}
mkReg :: Unique -> PrimRep -> Reg
mkReg = UnmappedReg
-getNewRegNCG :: PrimRep -> UniqSM Reg
+getNewRegNCG :: PrimRep -> NatM Reg
getNewRegNCG pk
- = getUniqueUs `thenUs` \ u ->
- returnUs (UnmappedReg u pk)
+ = getUniqueNat `thenNat` \ u ->
+ returnNat (UnmappedReg u pk)
-instance Text Reg where
+instance Show Reg where
showsPrec _ (FixedReg i) = showString "%" . shows IBOX(i)
showsPrec _ (MappedReg i) = showString "%" . shows IBOX(i)
showsPrec _ (MemoryReg i _) = showString "%M" . shows i
where
ex (MappedReg i) acc = IBOX(i) : acc -- we'll take it
ex _ acc = acc -- leave it out
+
+mappedRegNo :: Reg -> RegNo
+mappedRegNo (MappedReg i) = IBOX(i)
+mappedRegNo _ = pprPanic "mappedRegNo" empty
\end{code}
** Machine-specific Reg stuff: **
- Only ebx, esi, edi and esp are available across a C call (they are callee-saves).
- Registers 0-7 have 16-bit counterparts (ax, bx etc.)
- Registers 0-3 have 8 bit counterparts (ah, bh etc.)
-- Registers 8-15 hold extended floating point values.
+- Registers 8-13 are fakes; we pretend x86 has 6 conventionally-addressable
+ fp registers, and 3-operand insns for them, and we translate this into
+ real stack-based x86 fp code after register allocation.
+
\begin{code}
#if i386_TARGET_ARCH
gReg x = x
fReg x = (8 + x)
-st0, st1, st2, st3, st4, st5, st6, st7, eax, ebx, ecx, edx, esp :: Reg
+fake0, fake1, fake2, fake3, fake4, fake5, eax, ebx, ecx, edx, esp :: Reg
eax = realReg (gReg 0)
ebx = realReg (gReg 1)
ecx = realReg (gReg 2)
edi = realReg (gReg 5)
ebp = realReg (gReg 6)
esp = realReg (gReg 7)
-st0 = realReg (fReg 0)
-st1 = realReg (fReg 1)
-st2 = realReg (fReg 2)
-st3 = realReg (fReg 3)
-st4 = realReg (fReg 4)
-st5 = realReg (fReg 5)
-st6 = realReg (fReg 6)
-st7 = realReg (fReg 7)
-
+fake0 = realReg (fReg 0)
+fake1 = realReg (fReg 1)
+fake2 = realReg (fReg 2)
+fake3 = realReg (fReg 3)
+fake4 = realReg (fReg 4)
+fake5 = realReg (fReg 5)
#endif
\end{code}
#define edi 5
#define ebp 6
#define esp 7
-#define st0 8
-#define st1 9
-#define st2 10
-#define st3 11
-#define st4 12
-#define st5 13
-#define st6 14
-#define st7 15
+#define fake0 8
+#define fake1 9
+#define fake2 10
+#define fake3 11
+#define fake4 12
+#define fake5 13
#endif
#if sparc_TARGET_ARCH
#define g0 0
baseRegOffset (VanillaReg _ ILIT(6)) = OFFSET_R6
baseRegOffset (VanillaReg _ ILIT(7)) = OFFSET_R7
baseRegOffset (VanillaReg _ ILIT(8)) = OFFSET_R8
+baseRegOffset (VanillaReg _ ILIT(9)) = OFFSET_R9
+baseRegOffset (VanillaReg _ ILIT(10)) = OFFSET_R10
baseRegOffset (FloatReg ILIT(1)) = OFFSET_F1
baseRegOffset (FloatReg ILIT(2)) = OFFSET_F2
baseRegOffset (FloatReg ILIT(3)) = OFFSET_F3
#endif
baseRegOffset Hp = OFFSET_Hp
baseRegOffset HpLim = OFFSET_HpLim
+baseRegOffset CurrentTSO = OFFSET_CurrentTSO
+baseRegOffset CurrentNursery = OFFSET_CurrentNursery
#ifdef DEBUG
baseRegOffset BaseReg = panic "baseRegOffset:BaseReg"
baseRegOffset CurCostCentre = panic "baseRegOffset:CurCostCentre"
#ifdef CALLER_SAVES_HpLim
callerSaves HpLim = True
#endif
+#ifdef CALLER_SAVES_CurrentTSO
+callerSaves CurrentTSO = True
+#endif
+#ifdef CALLER_SAVES_CurrentNursery
+callerSaves CurrentNursery = True
+#endif
callerSaves _ = False
\end{code}
#ifdef REG_R8
magicIdRegMaybe (VanillaReg _ ILIT(8)) = Just (FixedReg ILIT(REG_R8))
#endif
+#ifdef REG_R9
+magicIdRegMaybe (VanillaReg _ ILIT(9)) = Just (FixedReg ILIT(REG_R9))
+#endif
+#ifdef REG_R10
+magicIdRegMaybe (VanillaReg _ ILIT(10)) = Just (FixedReg ILIT(REG_R10))
+#endif
#ifdef REG_F1
magicIdRegMaybe (FloatReg ILIT(1)) = Just (FixedReg ILIT(REG_F1))
#endif
#ifdef REG_HpLim
magicIdRegMaybe HpLim = Just (FixedReg ILIT(REG_HpLim))
#endif
+#ifdef REG_CurrentTSO
+magicIdRegMaybe CurrentTSO = Just (FixedReg ILIT(REG_CurrentTSO))
+#endif
+#ifdef REG_CurrentNursery
+magicIdRegMaybe CurrentNursery = Just (FixedReg ILIT(REG_CurrentNursery))
+#endif
magicIdRegMaybe _ = Nothing
\end{code}
-%************************************************************************
-%* *
-\subsection{Free, reserved, call-clobbered, and argument registers}
-%* *
-%************************************************************************
-
-@freeRegs@ is the list of registers we can use in register allocation.
-@freeReg@ (below) says if a particular register is free.
-
-With a per-instruction clobber list, we might be able to get some of
-these back, but it's probably not worth the hassle.
-
-@callClobberedRegs@ ... the obvious.
-
-@argRegs@: assuming a call with N arguments, what registers will be
-used to hold arguments? (NB: it doesn't know whether the arguments
-are integer or floating-point...)
-
\begin{code}
-reservedRegs :: [RegNo]
-reservedRegs
-#if alpha_TARGET_ARCH
- = [NCG_Reserved_I1, NCG_Reserved_I2,
- NCG_Reserved_F1, NCG_Reserved_F2]
-#endif
-#if i386_TARGET_ARCH
- = [{-certainly cannot afford any!-}]
-#endif
-#if sparc_TARGET_ARCH
- = [NCG_Reserved_I1, NCG_Reserved_I2,
- NCG_Reserved_F1, NCG_Reserved_F2,
- NCG_Reserved_D1, NCG_Reserved_D2]
-#endif
-
-------------------------------
freeRegs :: [Reg]
freeRegs
= freeMappedRegs IF_ARCH_alpha( [0..63],
- IF_ARCH_i386( [0..15],
+ IF_ARCH_i386( [0..13],
IF_ARCH_sparc( [0..63],)))
-------------------------------