+TODO in new NCG
+~~~~~~~~~~~~~~~
-Known bugs/issues in nativeGen, 000202 (JRS)
-~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+- Are we being careful enough about narrowing those out-of-range CmmInts?
-All these bugs are for x86; I don't know about sparc/alpha.
+- Register allocator:
+ - fixup code
+ - keep track of free stack slots
--- absC -> stix translation for GET_TAG and in fact anything
- to do with the packed-halfword layout info itbl field is
- pretty dubious. I think I have it fixed for big and little
- endian 32-bit, but it won't work at all on a 64 bit platform.
+ Optimisations:
--- Most of the x86 insn selector code in MachCode.lhs needs to
- be checked against the Rules of the Game recorded in that file.
- I think there are a lot of subtle violations.
+ - picking the assignment on entry to a block: better to defer this
+ until we know all the assignments. In a loop, we should pick
+ the assignment from the looping jump (fixpointing?), so that any
+ fixup code ends up *outside* the loop. Otherwise, we should
+ pick the assignment that results in the least fixup code.
--- When selecting spill regs, don't use %eax if there is a CALL insn
- (perhaps excluding calls to newCAF, since it doesn't return a
- result).
+- splitting?
--- Keep track of the stack offset so that correct spill code can
- be generated even if %esp moves. At the moment %esp doesn't
- move, so the problem doesn't exist, but there is a different
- problem: ccalls put args in memory below %esp and only move
- %esp immediately prior to the call. This is dangerous because
- (1) writing below %esp can cause a segmentation fault (as deemed
- by the OS), and (2) if a signal should be handled on that stack
- during argument construction, the args will get silently trashed.
+-- -----------------------------------------------------------------------------
+-- x86 ToDos
--- nofib/real/hidden gets slightly different FP answers from the
- via-C route; possibly due to exp/log not being done in-line.
+- x86 genCCall needs to tack on the @size for stdcalls (might not be in the
+ foreignlabel).
--- Possibly implement GLDZ and GLD1 as analogues of FLDZ and FLD1
- (x86), to reduce number of constants emitted in f-p code.
+- x86: should really clean up that IMUL64 stuff, and tell the code gen about
+ Intel imul instructions.
+
+- x86: we're not careful enough about making sure that we only use
+ byte-addressable registers in byte instructions. Should we do it this
+ way, or stick to using 32-bit registers everywhere?
+
+- Use SSE for floating point, optionally.
+
+------------------------------------------------------------------------------
+-- Further optimisations:
+
+- We might be able to extend the scope of the inlining phase so it can
+ skip over more statements that don't affect the value of the inlined
+ expr.
projects / ghc-hetmet.git / blobdiff