[project @ 2001-12-14 15:26:14 by sewardj]

[ghc-hetmet.git] / ghc / compiler / nativeGen / RegAllocInfo.lhs

diff --git a/ghc/compiler/nativeGen/RegAllocInfo.lhs b/ghc/compiler/nativeGen/RegAllocInfo.lhs
index 4cc220b..5d8f73b 100644 (file)
--- a/ghc/compiler/nativeGen/RegAllocInfo.lhs
+++ b/ghc/compiler/nativeGen/RegAllocInfo.lhs
@@ -148,15 +148,15 @@ regUsage :: Instr -> RegUsage
 interesting (VirtualRegI _)  = True
 interesting (VirtualRegF _)  = True
 interesting (VirtualRegD _)  = True
-interesting (RealReg i)      = _IS_TRUE_(freeReg i)
+interesting (RealReg i)      = isFastTrue (freeReg i)
 
 #if alpha_TARGET_ARCH
 
 regUsage instr = case instr of
     LD B reg addr      -> usage (regAddr addr, [reg, t9])
-    LD BU reg addr     -> usage (regAddr addr, [reg, t9])
+    LD Bu reg addr     -> usage (regAddr addr, [reg, t9])
 --  LD W reg addr      -> usage (regAddr addr, [reg, t9]) : UNUSED
---  LD WU reg addr     -> usage (regAddr addr, [reg, t9]) : UNUSED
+--  LD Wu reg addr     -> usage (regAddr addr, [reg, t9]) : UNUSED
     LD sz reg addr     -> usage (regAddr addr, [reg])
     LDA reg addr       -> usage (regAddr addr, [reg])
     LDAH reg addr      -> usage (regAddr addr, [reg])
@@ -236,8 +236,12 @@ regUsage instr = case instr of
     ADD    sz src dst  -> usageRM src dst
     SUB    sz src dst  -> usageRM src dst
     IMUL   sz src dst  -> usageRM src dst
+    IMUL64    sd1 sd2   -> mkRU [sd1,sd2] [sd1,sd2]
+    MUL    sz src dst  -> usageRM src dst
     IQUOT  sz src dst  -> usageRM src dst
     IREM   sz src dst  -> usageRM src dst
+    QUOT   sz src dst  -> usageRM src dst
+    REM    sz src dst  -> usageRM src dst
     AND    sz src dst  -> usageRM src dst
     OR     sz src dst  -> usageRM src dst
     XOR    sz src dst  -> usageRM src dst
@@ -266,10 +270,7 @@ regUsage instr = case instr of
     GLDZ   dst         -> mkRU [] [dst]
     GLD1   dst         -> mkRU [] [dst]
 
-    GFTOD  src dst     -> mkRU [src] [dst]
     GFTOI  src dst     -> mkRU [src] [dst]
-
-    GDTOF  src dst     -> mkRU [src] [dst]
     GDTOI  src dst     -> mkRU [src] [dst]
 
     GITOF  src dst     -> mkRU [src] [dst]
@@ -627,8 +628,12 @@ patchRegs instr env = case instr of
     ADD  sz src dst    -> patch2 (ADD  sz) src dst
     SUB  sz src dst    -> patch2 (SUB  sz) src dst
     IMUL sz src dst    -> patch2 (IMUL sz) src dst
+    IMUL64  sd1 sd2     -> IMUL64 (env sd1) (env sd2)
+    MUL sz src dst     -> patch2 (MUL sz) src dst
     IQUOT sz src dst   -> patch2 (IQUOT sz) src dst
     IREM sz src dst    -> patch2 (IREM sz) src dst
+    QUOT sz src dst    -> patch2 (QUOT sz) src dst
+    REM sz src dst     -> patch2 (REM sz) src dst
     AND  sz src dst    -> patch2 (AND  sz) src dst
     OR   sz src dst    -> patch2 (OR   sz) src dst
     XOR  sz src dst    -> patch2 (XOR  sz) src dst
@@ -652,10 +657,7 @@ patchRegs instr env = case instr of
     GLDZ dst           -> GLDZ (env dst)
     GLD1 dst           -> GLD1 (env dst)
 
-    GFTOD src dst      -> GFTOD (env src) (env dst)
     GFTOI src dst      -> GFTOI (env src) (env dst)
-
-    GDTOF src dst      -> GDTOF (env src) (env dst)
     GDTOI src dst      -> GDTOI (env src) (env dst)
 
     GITOF src dst      -> GITOF (env src) (env dst)
@@ -683,7 +685,7 @@ patchRegs instr env = case instr of
     JXX _ _            -> instr
     CALL _             -> instr
     CLTD               -> instr
-    _                  -> pprPanic "patchInstr(x86)" empty
+    _                  -> pprPanic "patchRegs(x86)" empty
 
   where
     patch1 insn op      = insn (patchOp op)
@@ -753,9 +755,8 @@ patchRegs instr env = case instr of
 Spill to memory, and load it back...
 
 JRS, 000122: on x86, don't spill directly above the stack pointer,
-since some insn sequences (int <-> conversions, and eventually
-StixInteger) use this as a temp location.  Leave 8 words (ie, 64 bytes
-for a 64-bit arch) of slop.
+since some insn sequences (int <-> conversions) use this as a temp
+location.  Leave 8 words (ie, 64 bytes for a 64-bit arch) of slop.
 
 \begin{code}
 spillSlotSize :: Int
@@ -775,18 +776,18 @@ spillSlotToOffset slot
    = pprPanic "spillSlotToOffset:" 
               (text "invalid spill location: " <> int slot)
 
-vregToSpillSlot :: FiniteMap Unique Int -> Unique -> Int
+vregToSpillSlot :: FiniteMap VRegUnique Int -> VRegUnique -> Int
 vregToSpillSlot vreg_to_slot_map u
    = case lookupFM vreg_to_slot_map u of
         Just xx -> xx
-        Nothing -> pprPanic "vregToSpillSlot: unmapped vreg" (ppr u)
+        Nothing -> pprPanic "vregToSpillSlot: unmapped vreg" (pprVRegUnique u)
 
 
-spillReg, loadReg :: FiniteMap Unique Int -> Int -> Reg -> Reg -> Instr
+spillReg, loadReg :: FiniteMap VRegUnique Int -> Int -> Reg -> Reg -> Instr
 
 spillReg vreg_to_slot_map delta dyn vreg
   | isVirtualReg vreg
-  = let        slot_no = vregToSpillSlot vreg_to_slot_map (getUnique vreg)
+  = let        slot_no = vregToSpillSlot vreg_to_slot_map (getVRegUnique vreg)
         off     = spillSlotToOffset slot_no
     in
        {-Alpha: spill below the stack pointer (?)-}
@@ -811,7 +812,7 @@ spillReg vreg_to_slot_map delta dyn vreg
    
 loadReg vreg_to_slot_map delta vreg dyn
   | isVirtualReg vreg
-  = let        slot_no = vregToSpillSlot vreg_to_slot_map (getUnique vreg)
+  = let        slot_no = vregToSpillSlot vreg_to_slot_map (getVRegUnique vreg)
         off     = spillSlotToOffset slot_no
     in
         IF_ARCH_alpha( LD  sz dyn (spRel (- (off `div` 8)))