[project @ 2003-06-03 09:37:14 by ross]

[ghc-hetmet.git] / ghc / compiler / nativeGen / RegAllocInfo.lhs

diff --git a/ghc/compiler/nativeGen/RegAllocInfo.lhs b/ghc/compiler/nativeGen/RegAllocInfo.lhs
index b54113b..e0377b8 100644 (file)
--- a/ghc/compiler/nativeGen/RegAllocInfo.lhs
+++ b/ghc/compiler/nativeGen/RegAllocInfo.lhs
@@ -400,11 +400,11 @@ regUsage instr = case instr of
     CMPL  sz reg ri    -> usage (reg : regRI ri,[])
     BCC          cond lbl      -> noUsage
     MTCTR reg          -> usage ([reg],[])
-    BCTR               -> noUsage
+    BCTR  dsts         -> noUsage
     BL    imm params   -> usage (params, callClobberedRegs)
     BCTRL params       -> usage (params, callClobberedRegs)
     ADD          reg1 reg2 ri  -> usage (reg2 : regRI ri, [reg1])
-    SUBF  reg1 reg2 ri  -> usage (reg2 : regRI ri, [reg1])
+    SUBF  reg1 reg2 reg3-> usage ([reg2,reg3], [reg1])
     MULLW reg1 reg2 ri  -> usage (reg2 : regRI ri, [reg1])
     DIVW  reg1 reg2 reg3-> usage ([reg2,reg3], [reg1])
     DIVWU reg1 reg2 reg3-> usage ([reg2,reg3], [reg1])
@@ -611,7 +611,8 @@ insnFuture insn
     BCC _ clbl             | isAsmTemp clbl -> NextOrBranch clbl
     BCC _ _ -> panic "insnFuture: conditional jump to non-local label"
     
-    BCTR -> NoFuture
+    BCTR (DestInfo dsts) -> MultiFuture dsts
+    BCTR NoDestInfo -> NoFuture
     boring     -> Next
 #endif {- powerpc_TARGET_ARCH -}
 \end{code}
@@ -833,11 +834,11 @@ patchRegs instr env = case instr of
     CMPL  sz reg ri    -> CMPL sz (env reg) (fixRI ri)
     BCC          cond lbl      -> BCC cond lbl
     MTCTR reg          -> MTCTR (env reg)
-    BCTR               -> BCTR
+    BCTR  dsts         -> BCTR dsts
     BL    imm argRegs  -> BL imm argRegs       -- argument regs
     BCTRL argRegs      -> BCTRL argRegs        -- cannot be remapped
     ADD          reg1 reg2 ri  -> ADD (env reg1) (env reg2) (fixRI ri)
-    SUBF  reg1 reg2 ri -> SUBF (env reg1) (env reg2) (fixRI ri)
+    SUBF  reg1 reg2 reg3-> SUBF (env reg1) (env reg2) (env reg3)
     MULLW reg1 reg2 ri -> MULLW (env reg1) (env reg2) (fixRI ri)
     DIVW  reg1 reg2 reg3-> DIVW (env reg1) (env reg2) (env reg3)
     DIVWU reg1 reg2 reg3-> DIVWU (env reg1) (env reg2) (env reg3)
@@ -916,23 +917,23 @@ spillReg vreg_to_slot_map delta dyn vreg
 
        {-I386: spill above stack pointer leaving 3 words/spill-}
        ,IF_ARCH_i386 ( let off_w = (off-delta) `div` 4
-                        in case regClass vreg of
-                              RcInteger -> MOV L (OpReg dyn) (OpAddr (spRel off_w))
-                              _         -> GST F80 dyn (spRel off_w) -- RcFloat/RcDouble
+                        in case regClass vreg of {
+                              RcInteger -> MOV L (OpReg dyn) (OpAddr (spRel off_w));
+                              _         -> GST F80 dyn (spRel off_w)} {- RcFloat/RcDouble -}
 
        {-SPARC: spill below frame pointer leaving 2 words/spill-}
        ,IF_ARCH_sparc( 
-                        let off_w = 1 + (off `div` 4)
-                            sz = case regClass vreg of
-                                    RcInteger -> W
-                                    RcFloat   -> F
-                                    RcDouble  -> DF
+                        let{off_w = 1 + (off `div` 4);
+                            sz = case regClass vreg of {
+                                    RcInteger -> W;
+                                    RcFloat   -> F;
+                                    RcDouble  -> DF}}
                         in ST sz dyn (fpRel (- off_w))
         ,IF_ARCH_powerpc(
-                       let sz = case regClass vreg of
-                                    RcInteger -> W
-                                    RcFloat   -> F
-                                    RcDouble  -> DF
+                       let{sz = case regClass vreg of {
+                                    RcInteger -> W;
+                                    RcFloat   -> F;
+                                    RcDouble  -> DF}}
                        in ST sz dyn (AddrRegImm sp (ImmInt (off-delta)))
        ,))))
 
@@ -945,22 +946,22 @@ loadReg vreg_to_slot_map delta vreg dyn
         IF_ARCH_alpha( LD  sz dyn (spRel (- (off `div` 8)))
 
        ,IF_ARCH_i386 ( let off_w = (off-delta) `div` 4
-                        in case regClass vreg of
-                              RcInteger -> MOV L (OpAddr (spRel off_w)) (OpReg dyn)
-                              _         -> GLD F80 (spRel off_w) dyn -- RcFloat/RcDouble
+                        in case regClass vreg of {
+                              RcInteger -> MOV L (OpAddr (spRel off_w)) (OpReg dyn);
+                              _         -> GLD F80 (spRel off_w) dyn} {- RcFloat/RcDouble -}
 
        ,IF_ARCH_sparc( 
-                        let off_w = 1 + (off `div` 4)
-                            sz = case regClass vreg of
-                                   RcInteger -> W
-                                   RcFloat   -> F
-                                   RcDouble  -> DF
+                        let{off_w = 1 + (off `div` 4);
+                            sz = case regClass vreg of {
+                                   RcInteger -> W;
+                                   RcFloat   -> F;
+                                   RcDouble  -> DF}}
                         in LD sz (fpRel (- off_w)) dyn
         ,IF_ARCH_powerpc(
-                       let sz = case regClass vreg of
-                                    RcInteger -> W
-                                    RcFloat   -> F
-                                    RcDouble  -> DF
+                       let{sz = case regClass vreg of {
+                                    RcInteger -> W;
+                                    RcFloat   -> F;
+                                    RcDouble  -> DF}}
                        in LD sz dyn (AddrRegImm sp (ImmInt (off-delta)))
        ,))))
 \end{code}