[project @ 1997-11-11 14:28:12 by simonm]

[ghc-hetmet.git] / ghc / compiler / prelude / TysWiredIn.lhs

diff --git a/ghc/compiler/prelude/TysWiredIn.lhs b/ghc/compiler/prelude/TysWiredIn.lhs
index c66d215..2c39168 100644 (file)
--- a/ghc/compiler/prelude/TysWiredIn.lhs
+++ b/ghc/compiler/prelude/TysWiredIn.lhs
@@ -46,21 +46,26 @@ module TysWiredIn (
        liftTyCon,
        listTyCon,
        foreignObjTyCon,
+
        mkLiftTy,
        mkListTy,
-       mkPrimIoTy,
-       mkStateTy,
-       mkStateTransformerTy,
-       tupleTyCon, tupleCon, unitTyCon, unitDataCon, pairTyCon, pairDataCon,
        mkTupleTy,
+       tupleTyCon, tupleCon, unitTyCon, unitDataCon, pairTyCon, pairDataCon,
        nilDataCon,
-       primIoTyCon,
        realWorldStateTy,
        return2GMPsTyCon,
        returnIntAndGMPTyCon,
+
+       -- ST and STret types
+       mkStateTy,
+       mkStateTransformerTy,
+       mkSTretTy,
        stTyCon,
        stDataCon,
-       stablePtrTyCon,
+       stRetDataCon,
+       stRetTyCon,
+
+       -- CCall result types
        stateAndAddrPrimTyCon,
        stateAndArrayPrimTyCon,
        stateAndByteArrayPrimTyCon,
@@ -77,6 +82,8 @@ module TysWiredIn (
        stateAndWordPrimTyCon,
        stateDataCon,
        stateTyCon,
+
+       stablePtrTyCon,
        stringTy,
        trueDataCon,
        unitTy,
@@ -255,8 +262,8 @@ wordDataCon = pcDataCon wordDataConKey fOREIGN SLIT("W#") [] [] [wordPrimTy] wor
 \begin{code}
 addrTy = mkTyConTy addrTyCon
 
-addrTyCon = pcDataTyCon addrTyConKey   fOREIGN SLIT("Addr") [] [addrDataCon]
-addrDataCon = pcDataCon addrDataConKey fOREIGN SLIT("A#") [] [] [addrPrimTy] addrTyCon nullSpecEnv
+addrTyCon = pcDataTyCon addrTyConKey   aDDR SLIT("Addr") [] [addrDataCon]
+addrDataCon = pcDataCon addrDataConKey aDDR SLIT("A#") [] [] [addrPrimTy] addrTyCon nullSpecEnv
 \end{code}
 
 \begin{code}
@@ -519,7 +526,8 @@ getStatePairingConInfo prim_ty
 %*                                                                     *
 %************************************************************************
 
-This is really just an ordinary synonym, except it is ABSTRACT.
+The only reason this is wired in is because we have to represent the
+type of runST.
 
 \begin{code}
 mkStateTransformerTy s a = applyTyCon stTyCon [s, a]
@@ -529,23 +537,17 @@ stTyCon = pcNewTyCon stTyConKey sT_BASE SLIT("ST") alpha_beta_tyvars [stDataCon]
 stDataCon = pcDataCon stDataConKey sT_BASE SLIT("ST")
                        alpha_beta_tyvars [] [ty] stTyCon nullSpecEnv
   where
-    ty = mkFunTy (mkStateTy alphaTy) (mkTupleTy 2 [betaTy, mkStateTy alphaTy])
-\end{code}
+    ty = mkFunTy (mkStatePrimTy alphaTy) (mkSTretTy alphaTy betaTy)
 
-%************************************************************************
-%*                                                                     *
-\subsection[TysWiredIn-IO]{The @PrimIO@ monadic-I/O type}
-%*                                                                     *
-%************************************************************************
-
-\begin{code}
-mkPrimIoTy a = mkStateTransformerTy realWorldTy a
+mkSTretTy alpha beta = applyTyCon stRetTyCon [alpha,beta]
 
-primIoTyCon
-  = pcSynTyCon
-     primIoTyConKey sT_BASE SLIT("PrimIO")
-     (mkBoxedTypeKind `mkArrowKind` mkBoxedTypeKind)
-     1 alpha_tyvar (mkPrimIoTy alphaTy)
+stRetTyCon
+  = pcDataTyCon stRetTyConKey sT_BASE SLIT("STret") 
+       alpha_beta_tyvars [stRetDataCon]
+stRetDataCon
+  = pcDataCon stRetDataConKey sT_BASE SLIT("STret")
+       alpha_beta_tyvars [] [mkStatePrimTy alphaTy, betaTy] 
+               stRetTyCon nullSpecEnv
 \end{code}
 
 %************************************************************************