/* -----------------------------------------------------------------------------
- * $Id: MachRegs.h,v 1.9 2000/07/11 15:26:33 sewardj Exp $
+ * $Id: MachRegs.h,v 1.12 2002/10/02 09:08:44 wolfgang Exp $
*
* (c) The GHC Team, 1998-1999
*
#define REG_R7 r20
#define REG_R8 r21
-#define REG_F1 fr14
-#define REG_F2 fr15
-#define REG_F3 fr16
-#define REG_F4 fr17
+#define REG_F1 f14
+#define REG_F2 f15
+#define REG_F3 f16
+#define REG_F4 f17
-#define REG_D1 fr18
-#define REG_D2 fr19
+#define REG_D1 f18
+#define REG_D2 f19
#define REG_Sp r22
#define REG_Su r23
#define REG_Hp r25
#define REG_HpLim r26
+#define NCG_SpillTmp_I1 r27
+#define NCG_SpillTmp_I2 r28
+
+#define NCG_SpillTmp_D1 f20
+#define NCG_SpillTmp_D2 f21
+
#endif /* powerpc */
/* -----------------------------------------------------------------------------
+ The IA64 register mapping
+
+ We place the general registers in the locals area of the register stack,
+ so that the call mechanism takes care of saving them for us. We reserve
+ the first 16 for gcc's use - since gcc uses the highest used register to
+ determine the register stack frame size, this gives us a constant size
+ register stack frame.
+
+ \tr{f16-f32} are the callee-saved floating point registers.
+ -------------------------------------------------------------------------- */
+
+#ifdef ia64_TARGET_ARCH
+
+#define REG(x) __asm__(#x)
+
+#define REG_R1 loc16
+#define REG_R2 loc17
+#define REG_R3 loc18
+#define REG_R4 loc19
+#define REG_R5 loc20
+#define REG_R6 loc21
+#define REG_R7 loc22
+#define REG_R8 loc23
+
+#define REG_F1 f16
+#define REG_F2 f17
+#define REG_F3 f18
+#define REG_F4 f19
+
+#define REG_D1 f20
+#define REG_D2 f21
+
+#define REG_Sp loc24
+#define REG_Su loc25
+#define REG_SpLim loc26
+
+#define REG_Hp loc27
+#define REG_HpLim loc28
+
+#endif /* ia64 */
+
+/* -----------------------------------------------------------------------------
The Sun SPARC register mapping
The SPARC register (window) story: Remember, within the Haskell
being the better part of valor, we also don't take %g4.
The paired nature of the floating point registers causes complications for
- the native code genertor. For convenience, we pretend that the first 22
+ the native code generator. For convenience, we pretend that the first 22
fp regs %f0 .. %f21 are actually 11 double regs, and the remaining 10 are
float (single) regs. The NCG acts accordingly. That means that the
following FP assignment is rather fragile, and should only be changed