[project @ 2004-08-13 13:04:50 by simonmar]

[ghc-hetmet.git] / ghc / includes / MachRegs.h

diff --git a/ghc/includes/MachRegs.h b/ghc/includes/MachRegs.h
index f183ffe..8297023 100644 (file)
--- a/ghc/includes/MachRegs.h
+++ b/ghc/includes/MachRegs.h
@@ -1,5 +1,5 @@
 /* -----------------------------------------------------------------------------
- * $Id: MachRegs.h,v 1.13 2002/12/11 15:36:37 simonmar Exp $
+ * $Id: MachRegs.h,v 1.16 2004/08/13 13:09:18 simonmar Exp $
  *
  * (c) The GHC Team, 1998-1999
  *
@@ -220,6 +220,47 @@
 #endif /* iX86 */
 
 /* -----------------------------------------------------------------------------
+  The x86-64 register mapping
+
+               callee-saves
+  %rax
+  %rbx         YES
+  %rcx
+  %rdx         (seem to be used as arg regs on x86-64)
+  %rsi         (seem to be used as arg regs on x86-64)
+  %rdi         (seem to be used as arg regs on x86-64)
+  %rbp         YES
+  %rsp         (unavailable - stack pointer)
+  %r8
+  %r9
+  %r10
+  %r11         
+  %r12         YES
+  %r13         YES
+  %r14         YES
+  %r15         YES
+  --------------------------------------------------------------------------- */
+
+#if x86_64_TARGET_ARCH
+
+#define REG(x) __asm__("%" #x)
+
+#define REG_Base  rbx
+#define REG_Sp    rbp
+#define REG_Hp    r12
+#define REG_R1    r13
+#define REG_SpLim r14
+#define REG_HpLim r15
+/* ToDo: try R2/R3 instead of SpLim/HpLim? */
+
+#define MAX_REAL_VANILLA_REG 1
+#define MAX_REAL_FLOAT_REG   0
+#define MAX_REAL_DOUBLE_REG  0
+#define MAX_REAL_LONG_REG    0
+
+#endif /* x86_64 */
+
+/* -----------------------------------------------------------------------------
    The Motorola 680x0 register mapping
 
    A Sun3 (mc680x0) has eight address registers, \tr{a0} to \tr{a7}, and
@@ -368,6 +409,8 @@
 #define REG_R7         r20
 #define REG_R8         r21
 
+#ifdef darwin_TARGET_OS
+
 #define REG_F1         f14
 #define REG_F2         f15
 #define REG_F3         f16
@@ -376,17 +419,25 @@
 #define REG_D1         f18
 #define REG_D2         f19
 
+#else
+
+#define REG_F1         fr14
+#define REG_F2         fr15
+#define REG_F3         fr16
+#define REG_F4         fr17
+
+#define REG_D1         fr18
+#define REG_D2         fr19
+
+#endif
+
 #define REG_Sp         r22
 #define REG_SpLim      r24
 
 #define REG_Hp         r25
 #define REG_HpLim      r26
 
-#define NCG_SpillTmp_I1        r27
-#define NCG_SpillTmp_I2        r28
-
-#define NCG_SpillTmp_D1        f20
-#define NCG_SpillTmp_D2        f21
+#define REG_Base        r27
 
 #endif /* powerpc */